Hi
I would like to build a frequency counter and use a Cpld for the divide by 10 logic.
Are 36 macro cells enough for that purposive ? A dived by 10 and 100 logic would be even better.
Unfortunately I am an absolute beginner and have no idea how much logic 36 macro cells could cover.
Cheers
Rubi
I believe you will need one macrocell for each divider bit (one register per bit), and probably one extra if you want features like reset.
In verilog you could do something like this:
module divider_counter (
clock_in,
divider_out
);
//global
input wire clock_in; //input clock signal
output wire divider_out; //divider output
//local
reg counter[9:0]; //10 bit register to hold the count
//output is toggled by last bit of counter
assign divider_out=counter[9];
initial //startup state, mostly for simulation sake
begin
counter=10'b000000000000;
end
always @ (posedge clock_in) //at positive edge of input clock
begin
counter<=counter+1;//increment 10 bit register by one each clock cycle
end
endmodule // End of Module counter
From there you can do things like add a reset. In another project I used 4 input pins to set the divider frequency by changing the reset value.
a larger cpld or fpga could act as the counter too, it is fairly simple to divide by 2 using just a few gates.
an 8 bit counter reset every 0.1ms would be able to count up to 2.5Mhz.
are you already using a micro?
what frequency range do you want to measure?
what type of accuracy do you require?
Hi Ian
Thank you for your help!
I will try that code.
@sqkybeaver
I just want to play a little with the CPLD dev board from Ian so I have no wish list for the specs.
Of course it would be possible to integrate the whole logic into a cpld or fpga but that would be way to difficult for me. I just want to combine a cpld with a micro controller.
The frequency range should be at least the whole shortwave band, but up to 2 meter or 70 centimetre would be even better but I have no idea how fast this cplds are.
Cheers
Rubi
for the top of the 70cm band(us) you will need to an input capable of 433Mhz, you probably know this,
the cpld on the dev boards will work to about 250Mhz i believe, a divide by 10 would be needed before signal is sent to cpld. you can try to find discreete logic that will work that fast or find a faster cpld.
what you want to do is great and i'd love to SE it work.
i have been using the built in counter on my scope(60Mhz limit) but i would like to get it up to 300Mhz(2x base) for 2M, when i start to work on an sdr project.
You will need to use some really fast cpld. The "standard" are capable of ~300mhz, not more. It also depends on your logic.
In general when dividing it can help to cascade dividers.
For example, to divide by 10, you want to divide by 2 first, then take the result of that operation and divide by 5. Likewise to get /100 with a /10 tap, just use two /10 dividers.
There's lots of material too be googled on dividers; a little patience will get you plenty of examples. You can do divide by 5 with three JK flops and some combinatorial logic. If you follow that with a D flop in a divide-by-2 arrangement you can get /10 with a 50% duty cycle.
This is something you can implement fairly easily with discrete high-speed logic, too.