Dangerous Prototypes

Looking at the DSO thread I get the feeling that we should go for something a lot simpler to start with. Why don't we make a wing that just have an 8bit parallel ADC and use the "scope" function of the sump client to view the waveform? The functionality is basic but it is still useful for debugging data uart/I2C/SPI for signal distortions or ADC input to MCU's.

You would only need:
ADC
Oscillator/ probably get it from fpga to sync with sample clock
buffer to fpga, not needed if we use 3v3 adc's
analogue buffer into adc

The whole thing can be done in the size of the logic input buffer wing.

I'm thinking from the situation where you are debugging an embedded application where you are really just interested in what the mcu is looking at, hence features like offset, gain and other usual features can be done without as most mcu's only see things from 0~3v3/5V.

I'm not an analogue guy so people are welcome to correct me. I just get the feeling from reading the thread that we are trying to shoot for the moon while we don't even have gun powder yet.

@hypernova: for a simple adc wing you need a) a "flash adc" converter , b) a signal output - an edge - from the optional wing pin indicating that the conversion shall happen at specific time (e.g. for sample and hold if any), but this is not necessary, c) a fast comparator and a potentiometer for setting the trigger level, the output from the comparator might be connected to a free OLS input pin (based on that edge the OLS starts to sample). That's all you need. There are [s:]hundreds[/s:] few of flash adc available, see for example MAX104-109 or a lot of flash adc from Analog Devices etc. The flash adc outputs the actual digital value "immediately" (the flash adc is built upon e.g. 256 comparators and some coding logic for 8 bit flash adc - thus it is not clocked, the propagation delay is few ns with fast adcs) so no specific adc clocking is needed (as it is needed with a successive aproximation or sigma-delta adcs). So you just set a sampling rate in OLS, start it, and you get the values of the analog signal directly into the OLS buffer (until OLS buffer is full) at that rate. You may run it @200MHz with OLS if the flash adc allows it (btw, most of flash adcs run at >>200MHz). The another question is the analog circuitry at the adc input, but that is another story..M.[attachment=0]

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I've tried looking at the ADC available locally (RS Taiwan) but the fastest Flash converter they have is 80MS/s, I would like go as fast as possible so I settled on this AD9215BRUZ-105 (http://http://taiwan01.rs-online.com/web/search/searchBrowseAction.html?method=getProduct&R=5386365). Looking at the timing diagram I'm thinking of an onboard clock supply so that while the results are ready at the rising edge the FPGA samples at the falling edge. In such configuration the sampling rate would depend on what the wing supply to the FPGA and would be adjusted using adjustable clock multipliers (jumper's, DIP switch...). I have never played with the external clock system on the OBLS though so I 'm just assuming this plan is workable.