I'm trying to simulate my first CPLD project for the Coolrunner II board, a 16-bit timer with a start and stop pulse. In case it isn't obvious, I've never worked with CPLDs before.
Here is the schematic of my project, and my VHDL testbench code.
http://bealecorner.org/best/measure/tim ... ematic.pdf (http://bealecorner.org/best/measure/time/CPLD-TIC/CPLD-TIC1-schematic.pdf)
http://bealecorner.org/best/measure/tim ... h1.vhd.txt (http://bealecorner.org/best/measure/time/CPLD-TIC/CPLD-TIC-testbench1.vhd.txt)
Here's the waveform I see from my test inputs:
http://bealecorner.org/best/measure/tim ... -180ns.pdf (http://bealecorner.org/best/measure/time/CPLD-TIC/CPLD-timing-180ns.pdf)
The counter starts and stops, and everything goes as expected until the reset pulse. START_S1B remains high, the top-left flipflop seems to ignore the reset, so the clock cannot be restarted after the first run. This is a synchronous reset and START_S1B should go low on the first clock rising edge during reset pulse... can anyone suggest why this happens?
That's really strange. I looked through the schematic and simulation, and did my best to read the test bench, it all looks correct to me. Shouldn't STOP_S1B also go low?
Ok, the two input flip-flops are clocked only by the two input signals (stop & start), not the CLK line. So they never see the reset pulse, since they aren't clocked at that time. So I want to use a jam-reset type FF for those first two FFs, not synchronous type as I have now.
Realized it just as I went to bed- I need more sleep...
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Edit: to be more precise, the FF I used was: FDR "Macro: D Flip-Flop with Synchronous Reset"
but what I want is: FDC “Macro: D Flip-Flop with Asynchronous Clearâ€
...from CPLD Libraries Guide version 13.1 (March 1 2011), p. 326 & 375: “cpld_all_scm.pdfâ€
http://www.xilinx.com/support/documenta ... ll_scm.pdf (http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/cpld_all_scm.pdf)
Ah, I thought the FFs reset independently of the clock. That makes sense then, thanks for the update.