Print Page - Cleaned up VHDL code + Meta + new RLE + Timing fix

Title: Cleaned up VHDL code + Meta + new RLE + Timing fix
Post by: kinsa on February 25, 2011, 07:55:36 am

Attached is a cleaned up version of the VHDL code with the following enhancements:

New SPI code, works with the latest PIC firmware (v3.0)
Working Metadata command (not sure if the values returned are correct)
New RLE code; n bit counters for n bit data width (except for 24 bits). Additional compression for cases with zero run lengths. RLE stop command is also implemented
Fixed the spurious triggers due to floating external trigger pin
Resolved timing issues

Also attached is the diff for Device.java that handles the RLE data and the fix for the before/after trigger capture.

Don't forget to regenerate the BRAM core before compiling the project.

Title: Re: Cleaned up VHDL code + Meta + new RLE + Timing fix
Post by: jack.gassett on February 25, 2011, 10:26:56 pm

Thank you kinsa,

I'll take a look and get it checked into github.

Jack.

Title: Re: Cleaned up VHDL code + Meta + new RLE + Timing fix
Post by: ian on February 26, 2011, 11:00:03 am

Thanks kinsa,

Great work! Now there are upgraded cores in both HDL languages.

Title: Re: Cleaned up VHDL code + Meta + new RLE + Timing fix
Post by: kinsa on February 27, 2011, 09:41:50 am

After reading dogbody's excellent documentation, here is the fix for the trigger point synchronization.

Note that for this VHDL code, RLE for 200 MHz sampling rate is not supported.

Title: SPI fixes
Post by: kinsa on March 07, 2011, 02:08:52 am

Missed the SPI synchronizer code.

The compiled bit file is also included.

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Other projects => Open Bench Logic Sniffer => Topic started by: kinsa on February 25, 2011, 07:55:36 am