The Bus Pirate currently has JTAG debugging support through OpenOCD, but that is overkill for programming CPLDs and FPGAs.
I dug up the old XSVF JTAG programming firmware based on the Xilinx XAPP058 app note and sample code (license unknown, so no distribution on the source until I clarify). I put just the XSVF and JTAG chain scan stuff into a new firmware that works with the v4 bootloader (attached). This firmware will quickly and easily program CPLDs and FPGAs (any brand that can export XSVF, or even SVF processed with the Xilinx converter) from the Bus Pirate v3.
It follows this simple protocol:
http://dangerousprototypes.com/docs/Bus ... SVF_player (http://dangerousprototypes.com/docs/Bus_Pirate_JTAG_XSVF_player)
We're working on a simple loader app now. It will take the XSVF output for CPLDs/FPGAs and hand it to the Bus Pirate.
This was spurred because urJtag doesn't want to work with teh XC9572XL breakout board, and we needed a way to test it. Not only that, but it should greatly expand the audience for the new boards.
Nice!
Awesome!! I can't wait to get one XC9500XL board
Got it working with the XC2c64a and the xc9500xl today.
Here's a screenshot, firmware, windows app, and app source (attachment on first post).
Cool! Just out of curiousity, could this also be used to program the FPGA in the OLS, without writing the flash?
The OLS is hard-wired for flash loading, and the JTAG is 2.5 volts (Bus Pirate is 3.3volts).
does it really need different fw ?:) couldn't it use OOCD1 binary protocol ?
Then the SVF player app would have to be smart. This uses a ready-made app-note on-PIC firmware to decode the SVF file. It was just a little bit of work. The application feeds the XSVF file in 4096 byte chunks, it doesn't know or care what the data is. It was only a marginal amount of work :)
It would be cool if we could read the contents of the CPLD/FPGA hihi <<-- i really need this option hehehe
of course you can, but not with
- svf player. Xilinx ise can do it.
can i use the xilinx ise with the buspirate?
No, just the parallel cables, USB pods, and some JTAG debuggers under LInux with a special alternative Xilinx driver.
Hi
can this parallel adapter be used with xilinx ISE to read from an FPGA?
http://www.sparkfun.com/products/8460 (http://www.sparkfun.com/products/8460)
[i found an old computer with a parallel port hihi]
I think that will probably work.
ganna try to build one hehehehe
Thanks every one!
You just have to understand that it is not like "normal" cpu programming. There is almost no way to get from "binary" file back to the logic it represents. Also, read lock can be set. So you are probably not going to get the data from the chip.
Actually the logic does not matter..my goal is to copy code from an existing FPGA and write it to a fresh FPGA to reproduce the old part
most fpga's have external flash rom for storing the configuration. Only few have non-volatile memory inside them. You should probably look into that first.
Hello Ian,
I have seen in a previous message of this thread that the source code of xsvf player cannot be provided.
Then could it be possible to get a version for Bus Pirate v4 ?
Or may be you can send me the source in order i adapt it to BPv4.
I have a BPv4 and would like to load an xsvf file in the XC9572XL dev board.
Regards
JM
Hi JM,
Source for the XSVF player is in our Dangerous Protrotypes SVN, and can be downloaded from our google code page as a .zip with all the other Bus Pirate stuff I think. If you have problems finding it please let me knwo, I'm not in the office but I can attached a link when I am back.
Hi.
Do you know whether is possible to reset CPLD via JTAG after programming, of course without power-cycling it?
Thanks!
It depends on the exact chip I guess. I know most CPLDs I have used (XILINX) are reset after programming without a power cycle.
hi everybody
what different between this device and Xilinx Platform Cable USB?can i expect this device do Xilinx platform cable work?
and if i want build one can i replace an avr usb to serial convertor(that i build later) with the ft232rl?