I'm not sure of the best buffer to use, or how many to include.
I've worked with the 74LVT573: 8bit, 4.4-4.9ns, input only:
http://www.mouser.com/Search/ProductDet ... 74LVT573WM (http://www.mouser.com/Search/ProductDetail.aspx?R=74LVT573WMvirtualkey51210000virtualkey512-74LVT573WM)
Jack has a board with the M74LCX16245: 16bit, 4.4ns, IO:
http://www.onsemi.com/pub_link/Collater ... 6245-D.PDF (http://www.onsemi.com/pub_link/Collateral/MC74LCX16245-D.PDF)
I don't know where to get the 16245, but the 573 is <50cents at Mouser.
Ideally, it would be nice to have all 32 channels of IO that SUMP supports, but if routing is really difficult I don't mind dropping a few.
I think some channels should be left buffer-free. They could be used with <3.3volts IO and with peripherals like a high-speed parallel interface ADC for o-scope functionality.
Speaking of ADC, there should be ENable, clock, power, and ground signals at the IO header if this is supported.
The M74LCX16245 is available at http://www.newark.com/jsp/search/productdetail.jsp?SKU=61K1020&CMP=AFC-OP&CMP=AFC-OP (http://http://www.newark.com/jsp/search/productdetail.jsp?SKU=61K1020&CMP=AFC-OP&CMP=AFC-OP) for $.61 in singles and $.35 at 1k.
I think cost and desired memory depth may dictate this. If we go with 16 channels we can increase the depth of our memory to 12K samples instead of 6K samples. Maybe, depending on price we can offer a board that has footprints for 32 buffered channels but offer a cheaper one populated with 16 buffered channels.
It will be easy to offer two versions of the logic analyzer bitstream. One that has 12K samples on 16 channels and 6K samples on 32 channels.
Let me quote Klaus Leiss post regarding the line buffers (http://http://whereisian.com/forum/index.php?topic=156.msg991#msg991) and continue the discussion here:
[quote author="LeissKG"]
[quote author="ian"]
I'm leaning against buffering the extra signals. It's possible to have an alternate upload for the FPGA that places these signals on some of the buffered pins, but having them unbuffered by default gives the cleanest, fastest signal path.
[/quote]
How about an external buffer. This would require a second small pcb with the Buffer ( or level translator ). It should not be that expensive, because
of the small size of the required pcb. It would also allow a longer cable between buffer and analyzer. I know that you don't need long data cables if
you can put the analyzer near the target. But this would also allow to substitute the buffer pcb with a level translator pcb if the logic on the target
requires this.
Klaus Leiss[/quote]
I agree with both Ians and Klaus' comments regarding on-board buffers ...
Up to this point I was proposing a compromise between "no buffers, only 3.3V tolerant" and "all buffered, 5V tolerant" to give users 5V capability right from the start - so only on the first 16 lines to keep the device in the targeted price range. The other reason was to keep an option for expansions on the 2nd 16 lines that would not be possible or only with restrictions if the lines would be buffered.
There are indeed a number of reasons to keep all I/O lines unbuffered (including the 4 dedicated signals Trigger_Out, Trigger_In, Clk_Out, Clk_In) in this first design:
1. The reasons Ian and Klaus gave: clean and fast signal path + flexibility/expandabilty
2. It will help to keep the cost down and the design to the basics without sacrifices (except for the 5V tolerance w/o a buffer expansion board)
3. Having 16 buffered and 16 unbuffered lines on the board poses certain timing/delay issues when working with more than 16 channels at high sampling rates (> 50MHz).
4. Gives even more flexibility for expansions/add-ons (on both headers/channels) and allows users to configure all I/O lines according to their needs.
We should look at a 16(+2) 5V/TTL/CMOS buffer expansion board to be released together with the LA and let the users decide if they need the 5V option ...
Just to sum up the buffers/transceivers we have been looking at so far:
1. M74LCX16245 (http://http://www.onsemi.com/PowerSolutions/product.do?id=MC74LCX16245) - Low-Voltage CMOS 16-Bit Transceiver
- 4.5ns max tpd
- suggested for 2.3 to 3.6V VCC Operation (VCC −0.5 to +7.0 according to data sheet)
- 5V Tolerant
- Interface Capability With 5V TTL Logic
- LVTTL and LVCMOS Compatible
- Supports Live Insertion and Withdrawal
- US$ 0.67 for 100+ qty. - in stock @ Digi-Key
2. NL27WZ126 (http://http://www.onsemi.com/PowerSolutions/product.do?id=NL27WZ126) Dual Buffer, 3 State High Enable
- 2.6 ns tpd (typical) at VCC = 5 V
- 2.3 V to 5.5 V VCC Operation
- LVTTL and LVCMOS Compatible
- US$ 0.33 for 100+ qty. - in stock @ Digi-Key
I think we dismissed the unidirectional 74LVT573 ...
Great propagation delay on the NL27WZ126, wish it came in a 16bit version.
Edit: Isn't the other chip good to 7volts or something? I was really impressed by that.
Hi,
These chips are really good at cost. But I think that TI has better parts like SN74LVC16T245 (http://http://focus.ti.com/docs/prod/folders/print/sn74lvc16t245.html).
Have a look,
Warm Regards,
Boseji
http://m8051.blogspot.com (http://m8051.blogspot.com)
[quote author="ian"]
Great propagation delay on the NL27WZ126, wish it came in a 16bit version.
[/quote]
For a logic analyzer the propagation delay is a meaningless number. If you use one buffer chip the difference in delay between bits is
usually to small to matter, a constant delay in the chip does not distort the measurement. If you must use more than chip the difference
between minimum and maximum delay generates the errors, since bits on different buffers that change at the same time seem to change on
different times. Another relevant parameter is the difference between rise and fall time in the buffer which should also be small.
My main reason for external buffers was other logic standards than 3.3V and 5.0V. For 3.3V and 5.0V an 3.3V Buffer with 5.0 V tolerant
I/O would suffice. But newer logic ( e.g. FPGA and CPLD ) has increasingly 2.5V or even 1.8V logic levels which we could not sample with
such a simple buffer even if the signal was slow enough. So the minimum necessary even with on board buffers is that the power supply for
the ( onboard ) buffers is on the probe connector. This way the user can build their own buffer / level translator boards if they need them.
But in any case it should be either no onboard buffers or buffers for all 32 channel. You could always populate only half for cost reasons.
Klaus Leiss
You are correct, I referred to the delta rise/fall time incorrectly as propagation delay.
Where are the board design files located? The last I saw there where no series termination resistor arrays on the inputs. If the design is going to be up in the 50Mhz+ range I would think ring reflections issues would start showing up, series termination resistors should help reduce ring and impedance match. Another idea I will just throw out there for fun is there could be no buffers on the main board and sell a separate buffer "wing".
LukeS, that's exactly what I am proposing now (see above): No buffers on the main board!
Instead we should release a 16-bit 5V tolerant buffer board (like Jacks Butterfly buffer widget) as a first wing/add-on board along with the LA main board. Everyone will be free to decide if they need 5V tolerance and if they want it for 16 or 32 channels. Beyond that it would keep all options open for a broad line of widgets/add-ons like voltage shifters/converters, DAs, ADs, pattern generators etc. Users could design widgets and customize them to their needs.