I'm in the market for a low cost I2C comms tester to ensure that a device under test correctly handles error conditions such as bus errors during reads / writes, badly formed commands , stress testing etc
Does the Bus Pirate have such a function or perhaps someone in the community has written an I2C test harness for the Bus Pirate?
Thanks in advance
Al
That's a really nice idea. The current hardware doesn't do that and is probably ill suited to do it properly (at full bus rates). The next version has an FPGA and it can definitely be adopted to test all conditions.
Do you have a list of tests to perform? I'm going to start on the I2C HDL for the FPGA very shortly, I can see if I can add it.
I am not able to post a reply due to some technical issue, but in response to your reply:
Thanks for the swift reply Ian :-) I guess I'd really just be trying to ensure that behavior outside of the protocol does not put the device under test into an undesirable state and to prove that if followed by a correctly formatted command the device under test recovers and responds appropriately. for example:
* Configure the I2C tester to send a valid packet to DUT but configure the tester to put in a STOP after 4 bits of the address
* Write a byte to the DUT, but corrupt it with a STOP condition after each bit in turn i.e. START + STOP, then START + first bit + STOP, then START + first 2 bits + STOP, ... until START + first 7 bits + STOP then issue a valid command to ensure that I2C comms are still okay.
* Same as above but for a READ
* Send a start condition then the address followed by the stop condition (no data) Followed by a read of the DUT to check all is well.
* Plus maybe also play with clock stretching, different clock speeds and maybe even play with pull-up R values
Cheers