Dangerous Prototypes

Dangerous Prototypes => Bus Pirate Development => Topic started by: ian on August 25, 2019, 03:03:26 pm

Title: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on August 25, 2019, 03:03:26 pm
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Last year Sjaak and I (mostly Sjaak!) tried to build a modern STM32-based Bus Pirate. Once we got deep into peripherals it was obvious that they weren't suited to a Bus Pirate like interface. This is actually something that crops up a lot. There was the revision B2 silicon bug in the 24FJ64GA002 that forced us to use software I2C. The I2C peripheral in the STM32 needs to know one byte in advance when the transaction will end, something impossible to guess consistently based on human-speed user input. We keep running into situations where the hardware peripherals are limited or down-right standing in our way.

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When the ICEstorm open source Lattice ICE40 stuff came out, Sjaak suggested we just build our own peripherals in an FPGA and access it through the 16 bit static ram interface on the biggest STM32F103. The Bus Pirate "Ultra" was born.

This summer we've been hacking on V1a. It's the same basic concept as previous Bus Pirates:
But we also have some extra goodies:

Currently everything is in one git repo (https://github.com/DangerousPrototypes/Bus_Pirate_Ultra), but I'll get the firmware, HDL, and hardware separated out today.

Firmware status
These things are all working to some extent. We're not to the point of actually talking to any chips with our SPI peripheral, but we can control it and capture the bus activity using the built in logic analyzer. It's so cool!

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Check this out! This is Bus Terminal, a really crappy Qt program we hacked together. Type commands into the Bus Pirate terminal, and every time you hit <enter> the Bus Pirate runs the commands while capturing the signal. The logic graph updates instantly! No setting triggers, no arming, no trying to get a logic analyzer probe stuck in an odd little place. Boom! You type and then you see what happens! This will be even cooler when we get a driver written for SigRok and have live protocol decoding as well :)

Look at that timing in the logic graph. It is tight, and it is clocked exactly the same each time. That's because the FPGA unbinds us from the USB housekeeping constantly going on in the MCU.

HDL status

Getting the logic analyzer working was our first priority, and it probably took longer than anything else. Once it was done though, wow, what a delightful development experience. Not only can we see live what is happening with the pins, we can also point the logic analyzer to things inside the FPGA to debug the HDL.

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This is the basic outline of how it all works. Between the MCU and FPGA there is a 16 bit bi-directional data bus and 6 (?) bits of address pins. The memory controller in the MCU reads and writes through this bus just like it's a local system register. The registers in the FPGA are attached to things like pin mode (enabled, in/out, open drain, etc), logic analyzer stuff, and speed settings.

One register, currently register 7 but eventually register 0, is connected to a 512 word FIFO buffer. The buffer feeds a state machine with commands like write xbits, read xbits, delay, halt, enable/disable logic analyzer. Our current development firmware loads up the FIFO with commands, then enables the state machine. Because this all happens inside the FPGA, everything is exactly the same each time a command is run, down to the clock tick! Sometimes we think the logic analyzer is stuck because nothing changes between runs.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on August 25, 2019, 03:28:23 pm
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You may have noticed that most of the components on the bottom edge of the v1a are not populated. That's because when we started working the design it was obvious that we could push it a lot further with a few tweaks.

First, we dropped the ADC, Vpu, and 3.3V pins. We added 3 more IO pins, giving us 8 IO total. What do you know, that matches the 8 channels available from the logic analyzer :)

Instead of measuring voltage through a dedicated ADC pin, we used an 74xx4015 8:1 analog mux and a op-amp to add low impedance voltage measurement to ALL the IO pins. Woot!

Next, we used the DAC from the MCU to margin a Microchip voltage regulator to get a 0.8volt to 5.0volt adjustable output power supply. This new "Vout" pin replaces the 5volt pin. Bam!

Finally, we double up the 4066s to add optional pull-up resistors to all 8 IO pins. The pull-ups are now powered by the output of the adjustable power supply, or by an external voltage applied to Vout. All the outward-facing buffer logic is also powered in the same way using the Vout pin.

1. MOSI
2. CLOCK
3. MISO
4. CS
5. AUX
6. AUX2 (formerly ADC)
7. AUX3 (formerly Vpullup)
8. AUX4 (formerly 3.3Volts)
9. 0.8-5.0Vout/Vref (formerly 5.0Volts)
10. GND

This is our new pinout  8) Routing on this board is still in progress, but we hope to be stuffing it by early September.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on August 26, 2019, 05:43:23 pm
I divided the repo into separate repos so it's less annoying for everyone:

Firmware (old repo): https://github.com/DangerousPrototypes/Bus_Pirate_Ultra
Hardware: https://github.com/DangerousPrototypes/BusPirateUltraHardware
HDL (for FPGA): https://github.com/DangerousPrototypes/BusPirateUltraHDL
Bus Terminal: https://github.com/DangerousPrototypes/BusTerminal

Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: USBEprom on August 26, 2019, 11:04:59 pm
Hi Ian.
Really impressive device, it could have been called Bus Pirate v5!
I hope it will soon be developed and marketed.

Be seeing you.

U.Sb
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: tayken on August 29, 2019, 05:50:41 pm
I divided the repo into separate repos so it's less annoying for everyone:

Firmware (old repo): https://github.com/DangerousPrototypes/Bus_Pirate_Ultra
Hardware: https://github.com/DangerousPrototypes/BusPirateUltraHardware
HDL (for FPGA): https://github.com/DangerousPrototypes/BusPirateUltraHDL
Bus Terminal: https://github.com/DangerousPrototypes/BusTerminal

Real nice. As this is a single project, I would've arranged things a bit differently, kinda in a tree structure so that I just need to pull one repo to access everything. Sth like this:
Code: [Select]
Bus_Pirate_Ultra (repo)
├── firmware/
│      ├── firmware
│      ├── files
│      └── ...
├── fpga/ (or hdl/)
│      ├── HDL
│      ├── files
│      └── ...
├── hardware/
│      ├── hardware
│      ├── files
│      └── ...
└── terminal/
        ├── software
        ├── files
        └── ...

Also one questıon: Is it possible to increase the number of address lines? 6 lines gives us only 64 registers, we will probably hack the living bejeezus out of it real soon with additional stuff. If we have pins available, we can bump it up to 7 (128 registers) and use the 8th pin as R/W line?
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: tayken on August 29, 2019, 06:06:56 pm
Finally: Damn, that looks cool! Can't wait to get my hands on one!  :D
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on August 30, 2019, 08:57:29 am
I agree with you on the single repo and structure. There were a couple motivations to separate the repos. The firmware includes the printf and libopencm3 submodules, so every push/pull needs a few extra click and switching branches results in lots of (ignorable) error messages. Another big one is that the automated build script is a bit dumb about when files change, so it makes the firmware and HDL every time there's any upload to the repo which is a bit obnoxious.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on August 30, 2019, 09:09:58 am
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V1b is off to the board house. Quite a few passives on the bottom layer. We're doing a basic test of the current schematic on a two layer board, then we'll move to four layers for the final/next board. We'll definitely add as many more address pins as possible when we move to 4 layers.
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I've been playing with displays :) I feel like a small e-ink is the perfect pinout label, but the IPS LCDs are great too.
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I'm leaning towards e-ink because I don't want to get bogged down writing a flashy display interface, but I can think of so many things that could be updated on an LCD in real time (state of each pin, voltage of each pin, bus contention, etc).
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on August 30, 2019, 10:29:16 am
The next thing we probably need to think about is a daughterboard (pirate sail? ugh, kill me :P) for the IPS LCD and eInk displays.
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This is the schematic for the eink demo board. We are using R2=3ohm, so we don't need the resistance select or R3.
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The retaining clip holder of the connector seems to be 1.6mm.
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My initial thought is a daughterboard that mounts to the two holes over the io connector. If we cut out the PCB around the connector retaining mechanism I believe the display will lay completely flat on a 1.6mm thick PCB. It seems the standard thing to do with the display flexpcb connector is to have a slot in the board and bend it under to the bottom side. all the components would be on the bottom and the display lays flat.

Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on August 30, 2019, 11:05:52 am
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We'll work up something like this for both types of displays.

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I have IPS LCDs from two suppliers that seem reliable (able to get the display long term without driver changes). I like this one best, but I still don't have the full datasheet. This is from a rather large display factory.
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This one I have full datasheets for, but the build quality seems a bit lower than the other one (haven't seen the display in action to judge though). This is from a distributor, not a factory, as far as I can tell.
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The eInk uses a 24 pin 0.5mm connector (https://www.buydisplay.com/download/connector/ER-CON24HT-1.pdf). Both IPS LCDs use a 12 pin 1mm connector (https://www.buydisplay.com/download/connector/ER-CON12HB-2.pdf).

The LCDs have different pinouts, which is a pain, but at least the daughterboard only needs two connectors and a transistor or fet for switching the backlight from PWM.

Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on August 30, 2019, 12:12:23 pm
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Great! The TJC8A-10WA lock mechanism is 1.55mm tall. A 1.6mm thick PCB daughterboard with a notch will let the display lay flat against the edge of the connector.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on September 05, 2019, 10:38:20 am
I got datasheets (attached) from both of the 2inch LCD manufacturers. They actually have the same pinout, the text in one was just really messed up. So we'll only need a single carrier board to test both displays.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on September 09, 2019, 12:09:45 pm
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The display datasheets are a mess. It's a long story that might make a good blog post some day. The displays connector is soldered to the PCB, it doesn't use a ZIF socket. Here's the display carrier board, we'll send this off soon.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on September 10, 2019, 05:42:22 pm
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This is a little test board that plugs into the Bus Pirate header. The LEDs show if the pin is high or low to make debugging easier. We also brought out Vout to measure, or to use an external Vref with the buffer.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: Sjaak on September 11, 2019, 07:20:28 pm
I uploaded basic UART to the HDL repo earlier this week: https://github.com/DangerousPrototypes/BusPirateUltraHDL/tree/master/components/uart

Currently it only accept n-8-1 (no parity, 8 bits, 1 stopbit). The baudrate is clk/4 in order to make it reliable work (I hope :D)

things to add (in random order):
- odd/even parity
- baudrate detection
- 5-9 bits (or 8 if parity is involved)
- 1, 1.5 or 2 stopbits
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on September 11, 2019, 08:08:37 pm
Nice. It simulates for me :)

I believe we need to split the protocol handing in the MCU into separate "compiling" and "result" functions, then we can start hooking up all the protocols.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on September 11, 2019, 08:09:55 pm
Thank you for posting. I noticed the notification email doesn't include the reply text. I'll fix that.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: tayken on September 16, 2019, 07:42:36 pm
I uploaded basic UART to the HDL repo earlier this week: https://github.com/DangerousPrototypes/BusPirateUltraHDL/tree/master/components/uart

There are OpenCore versions of these, maybe you guys can use some of these?
https://opencores.org/projects?expanded=Communication%20controller
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on September 21, 2019, 12:05:28 pm
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I stuffed as much of the new board as I could. I don't have 2 of the chips, or any of the 0402 components.

Here's a list of changes and bugs I noticed:

@tayken you're right, we're gonna raid that so hard :) Also the icotools from icestorm developer have some really solid peripherals.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on September 21, 2019, 01:09:24 pm

Currently we are using MCP1824 adjustable as the Vout. Confirmed in datasheet the test conditions are 4.7uf ceramic. As low as 1uF would work, but let's go with 4.7uF on input and output.

We are using MCP1801 for the 3.3volt and 1.2volt supplies. This is a 150ma LDO with enable. We really don't need the enable, but I like the SOT-23-5 package because it gives almost twice as much contact for thermal dissipation to the PCB. It will take some before we have a realistic power budget, but I believe we should target 200-250ma on both rails for development. The other issue is the display and LEDs, that's gonna eat up a bunch (60-80mA).


MCP1700 (http://ww1.microchip.com/downloads/en/DeviceDoc/MCP1700-Low-Quiescent-Current-LDO-20001826E.pdf) is cheap, no enable, 250mA. The three pin sot-23 package is limiting, but there is a SOT-89 between the SOT223 and SOT23 in size. The datasheet suggests 1uF on in and out, but more on input is possible. How about 1uF on output and 4.7uF on input to keep the BOM smaller?

Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: Sjaak on September 23, 2019, 08:43:09 pm
There are OpenCore versions of these, maybe you guys can use some of these?
https://opencores.org/projects?expanded=Communication%20controller

It is also an exercise for me to understand VHDL/Verilog. I also have the idea that I'm in control in making the peripheral the way I want and not optimized for a specific architecture or to emulate an existing chip. the fun stuff is flexibility of fpga (also the hard part :D)
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on September 25, 2019, 09:45:38 am
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The display carrier boards arrived. Fit is pretty good.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on September 25, 2019, 02:27:25 pm
Display board updates:

v1.0b updates:

Soldering 0402 is fun! Even easier than 0603! Why did I avoid it for so long?
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 05, 2019, 05:18:32 pm
Updated v1c PCBs are in git with most of the fixes above. Here's what we came up with in review:

*C73 should be 1uF
*VR1 to MCP1700-33 SOT-89? 4.7uF input capacitor, 1uF output cap (C28) (not VR2 for now...)
*VR2 needs the 4.7uF input cap
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*Replace MCU ADC1 with ADS7041 connected to FPGA. Add C+R filter (C=1.5nF NPO/COG, R=25R)
*all of the chip Ux including the VRs
*logical part numbering. like e.g. in the buffer part of BPU we can name them in group like R1xx, C1xx, U1xx
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 06, 2019, 10:59:12 am
We're going to handle IO pin voltage measurements with a small SPI ADC running constantly at 1MSPS.

The only other ADC measurements we have are Vusb and Vout/Vref. Vout/Vref will need to be shown on the display, so it would make sense to keep that in the FPGA too.

How about we swap the 4051 with a 4067? It's 16bits mux and only needs one additional control line. Then connect Vout and Vusb measurement to the mux? That eliminates 4 2 resistors (and 2 constant loads to ground).

@Sjaak pointed out that we are not measuring 1.2v for the self test. This should be measured from the MCU because if it is defective we wouldn't be able to measure it from the FPGA.

Also noted that there is a SC-70 version of the op-amps, and all 0.1uF caps can become 0402 at this point to save space.

*Switch 74HCT4051 with 74HCT4067
*Connect Vusb and Vout to 4067, remove connections to MCU ADC pins leave the redundant connections
*Connect MCU ADC pin directly to 1.2volt rail for measurement (no R divider needed)
*0.1uF can become 0402 as needed
*Consider sc-70 op-amps
*R805 and R806 to 50K
*Move or duplicate D200 on pin Z of the 4067

*Edit: it doesn't make sense to measure Vusb this way. It's even questionable to measure anything that might be >Vusb this way... At minimum we should clamp the input to the 4067 with a diode. Maybe move the diode protecting the op-amp to before the 4067?
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 06, 2019, 12:33:10 pm
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LM4040 (http://www.ti.com/lit/ds/symlink/lm4040-n.pdf) is a 3.0V shunt reference. We could use this for the ADC AVDD. That would give us a max of 6.0volts instead of 6.6volts. If we take 8 bit measurements from the ADC then we would have a resolution of 0.0234volts/bit vs 0.0257volts/bit. Don't know if it's worth it, but it might be "proper" :)

I assume we'll take 8 bit measurements because the 10bit ADC only has 9.x bits or real resolution, and if we have 10 things to measure (DIO1-8, Vout, Vusb) that will consume 5 of our 16bit read registers.

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The ADC uses max 200uA AVDD at full speed, the shunt can supply 100uA (minimum) to 15mA.

Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 06, 2019, 12:38:29 pm
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MCP1253 (https://www.microchip.com/wwwproducts/en/MCP1253) could be used to get a really solid 5v supply from Vusb, even if Vusb is above or below 5volts (4.4v-5.25 allowed by USB spec). Currently we power the 4066 (pull-ups), 4051 (4067) (analog mux), and the 2 op-amps from Vusb. I guess my concern would be ripple from the charge pump on the op-amps and analog mux.

U301 (adjustable power supply op-amp used for margining) could be powered by 3.3volts instead. We'd need to check for linearity issues close to the rails.

U201 (op-amp buffering voltage measurements) needs to be as close to 5V as possible, but powering this op-amp from either Vusb or a rippling charge pump sounds like an awful idea :) I'll think this through a little more.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 07, 2019, 12:07:30 pm
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The programmable output power supply works great! 0.8 to 5.0v output with 12bits of resolution!

Code: [Select]
                        temp=askint("value", 1, 0xFFFFFFFF, 1000);
rcc_periph_clock_enable(RCC_DAC);
                        gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4);
                        dac_disable(CHANNEL_1);
                        dac_buffer_disable(CHANNEL_1);
                        dac_disable_waveform_generation(CHANNEL_1);
                        dac_enable(CHANNEL_1);
                        dac_set_trigger_source(DAC_CR_TSEL1_SW);

                        dac_load_data_buffer_single(temp, RIGHT12, CHANNEL_1);
                        dac_software_trigger(CHANNEL_1);

                        //enable the VREG
                        gpio_set(BP_PSUEN_PORT, BP_PSUEN_PIN);
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 07, 2019, 04:46:44 pm
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Voltage measurements on all pins through the multiplexer is working :) The multiplexer is controlled by the FPGA, but the MCU is still doing the analog measurement. In the next revision this will all be folded into the FPGA using the ADS7042 (http://www.ti.com/product/ADS7042).
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: soupie on October 08, 2019, 10:07:30 am
I'd be interested in seeing this act as a frequency counter, for signals on the analog input.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 10, 2019, 10:43:05 am
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SPI peripheral is working :) We defo need a warning about no voltage on the buffers/Vout/Vref... I always forget to power up and think there's a bug. Currently we're processing everything in three loops, but I think I'll reduce that back to 2 loops for the time being (pre/post processing).

The display connectors and cables should be here in an hour or so. I've already written the display code, will solder up the boards and test that next.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 10, 2019, 03:45:58 pm
This is the BOM for v1b (the current latest prototype). It is a bit of a mess, lots of different footprints for the same part. This is cleaned up in v1c but the numbering is totally changed. For parts with missing values you can refer to my post up thread (http://dangerousprototypes.com/forum/index.php?topic=10316.msg70133#msg70133).
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: electroniceel on October 10, 2019, 09:17:11 pm
Have you seen this project: https://github.com/GlasgowEmbedded/glasgow (https://github.com/GlasgowEmbedded/glasgow)?

It originally even had "Bus Pirate + Bus Blaster + Logic Sniffer" as description, but that is now removed.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 10, 2019, 09:42:50 pm
Nice! I will check it out in detail. Glad the concept Lives on!
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: Squonk on October 10, 2019, 10:00:44 pm
Do you have an idea of the retail price yet?

The BP3 is $30, but I am afraid that with all the added stuff, the Ultra will be more than twice this tag.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 10, 2019, 11:50:44 pm
We're just playing at this point. So many great new tools! Sjaak and I like to have something to banter about over bara :)
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 11, 2019, 09:27:45 am
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With a slight change we can have significantly more address lines. We'll need to move the display CS and MCUVPU, but A6,7,8,9,11 are already connected to FPGA. If we move those two pins we would have double the address space.

The other thing to finalize:
1. master reset on one GBIN 0/2/4/6 (that isn't also a dedicated MCU interrupt)
2. a EXTI0 to EXTI4 portpin to FPGA with dedicated interrupt that is not on a GB pin of the FPGA
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 11, 2019, 03:00:53 pm
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Today we finished stuffing the first Bus Pirate "Ultra" v1b board. This includes the updates we posted this week, and a few other improvements from v1a:

The new power supply and voltage measurement concept are both tested and working on the new hardware. The new USB C connector is extremely solid and is a dream to solder, we'll never look back.

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Next we'll work on getting the display going. So far it powers up and no smoke escapes.

Eagle files for v1b (https://github.com/DangerousPrototypes/BusPirateUltraHardware) are in the git repo.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 11, 2019, 05:59:23 pm
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The IPS LCD panel is working. It's kind of strange, the vendors gave us very different sample initialization code. Only one sample code worked, but it worked with every panel we bought.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 14, 2019, 11:32:15 am
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Got the display to show the mock-up image. The background is done in Photoshop, then uploaded to the LCD. The working version won't look this nice because the MCU won't be able to do the same level of anti aliasing on the text and we'll have to fake the alpha blending.

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Most LCD fonts are 1bit per pixel bitmaps. 1 is the text color, 0 is the background color. This kind of font looks jagged on an LCD.

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Anti aliasing makes the letters a bit fuzzy around the edges and gives an overall nicer look.Anti aliasing in real time on the MCU will take too many resources. Instead, we made a pre-anti aliased font that uses 2bits per pixel and a four color lookup table. The resulting font takes twice as much space as a one bit font, but the extra bit (two extra colors) are used for those nice fuzzy edges.

I put an open source font on a grid in Photoshop and anti aliased it. Then I changed it to indexed color and a custom pallet of 4 colors (text, background, and 2 shades of grey for the anti aliasing).

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Finally, I added some code to the Bus Terminal software to extract the characters and color table  reduce to indexed color with a custom pallet, then extract each character to a bitmap.

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This is an example of different anti aliasing methods (sharp/crisp/strong/smooth) using 2 bits/pixel and a color lookup table. The line on the bottom has no anti aliasing. Without anti aliasing the bottom line is jagged and rough. The other lines add one bit (two indexed colors) for anti aliasing and look remarkably better, even without tweaking.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 15, 2019, 06:29:25 pm
We're in the process of tweaking the pin connections. It should be finalized tomorrow.

We're going to use a 0.5mm fpc connector for the display. A few other tweaks for the display board:
*Fpc is 1:n so the connector pins need to be reversed
*Add caps (0.1uf, 10uf) to power supply
*Update transistor part number
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 16, 2019, 02:02:12 pm
Test firmware for Sjaak. Various FPGA stuff is disabled so it will boot...
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 16, 2019, 04:08:36 pm
ELF version for Sjaak :)
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: carpas on October 16, 2019, 07:23:36 pm
Have you seen this project: https://github.com/GlasgowEmbedded/glasgow (https://github.com/GlasgowEmbedded/glasgow)?

It originally even had "Bus Pirate + Bus Blaster + Logic Sniffer" as description, but that is now removed.
Very interesting project. It has many pins, I think the new bus pirate must have at least 16 I/O pins, 32 is better.
Another interesting function is "automatically determine unknown JTAG pinout", with new bus pirate is very hard add it.
Not has uC ARM, but a 8051, I don't know which is better.
I hope the price will not be more than 50$.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 16, 2019, 07:32:31 pm
Thanks for checking out our progress. We've already used all the pins on a 144 pin FPGA, so we won't be able support more IOs without a bigger bga chip (if one exists?). We'll think about more pins later, but 8 serves our initial purpose well.

I'm curious why we couldn't support the JTAG auto detect? I assume it's just a JTAG boundary scan on various pins until some kind of bits are detected. I'm sure we can do that.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 16, 2019, 07:38:30 pm
In terms of price, this is not gonna be in the 30 to 50 range until we move to a cheap Chinese SoC. There are probably $50 of parts on the board plus a 4 layer PCB and the whole thing has to be certified and probably shipped in a case.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: carpas on October 17, 2019, 11:48:17 am
I'm curious why we couldn't support the JTAG auto detect?
I have a router with 20 pin header which should be a jtag, has not standard pinout, I tried many "jtag finder" none has had success.
All devices which I've seen, have more than 8 pins: 30, 24. So with only 8 pins I don't know how bus pirate detect all pins.

I'm sure we can do that.
Good...  :D
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 17, 2019, 11:52:43 am
That's an interesting use case, and not one I'm familiar with. No we would not be able to probe 20 pins at once. I don't see how we get more than 8 IO with the current design. But we can definitely probe an 8 pin header :)
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: electroniceel on October 17, 2019, 11:37:53 pm
Very interesting project. It has many pins, I think the new bus pirate must have at least 16 I/O pins, 32 is better.
The Glasgow revC, the one that will be manufactured first, has 16 pins (2 ports of 8 pins each). There will be a revD with 32 pins in the future. This makes it easy to do not only the JTAG scanning you mentioned, but also interface wide parallel busses, use it as a wide bus logic analyzer, read/write parallel EEPROM or flash,...

Another interesting function is "automatically determine unknown JTAG pinout", with new bus pirate is very hard add it.
Not has uC ARM, but a 8051, I don't know which is better.
The point of using the Cypress FX2 is not the 8051 core that is embedded, but that it offers really fast usb transfers from the FPGA. I get around 340 MBit/s of real data througput when running the transfer benchmark on my Glasgow prototype. The STM32F103 on the BusPirate Ultra can only do USB FullSpeed (12 MBit/s theoretical max.). Even STM32F4 with a separate ULPI PHY don't get near the transfer rate of the Cypress FX2.

The Glasgow and BusPirate Ultra have a bit of a different concept there: the BusPirate Ultra will usually do the processing and data conversion on the hardware, probably a smaller part in the FPGA and most of it in the STM32. The data is then transfered to the PC over a emulated serial port, with the same or similar protocol as the previous versions of the BusPirate. At least this is what I understood from Ian's posts here.

The Glasgow will instead usually use a custom software on the host PC. This software consists of Applets that configure the FPGA for the current task (gateware) and also a part that converts the data on the PC. So the 8051 microcontroller on the hardware has much less to do. Also the FPGA gateware is not a collection of generic pre-synthesized gatewares, but directly synthesized for the task and configuration at hand, making it more efficient. The downside is that you need to install the Glasgow software stack (Python, nMigen, Yosys, nextpnr) on the host PC, while the BusPirate just needs a USB CDC serial driver.

I hope the price will not be more than 50$.
The price for the Glasgow will probably be in the $150-$200 range. It will be available from here soon: https://www.crowdsupply.com/1bitsquared/glasgow (https://www.crowdsupply.com/1bitsquared/glasgow)
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 18, 2019, 09:36:10 am
@electroniceel It is an absolutely killer project! You do really good work!

We're going to add a second USB bulk end point for non-terminal stuff that basically just gives access to the FPGA registers and FIFO, but it will never come close to the speed you get with the FX2. That's going to tear through some flash chips :)
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 23, 2019, 09:28:52 am
X

v1c is technically done, but we came up with some hot last minute additions. We'll probably skip this board and send out the updated version with the additional features at the end of the week.

New in v1c:
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 24, 2019, 05:03:58 pm
X

Wheee! I believe this is the first full test of the "Ultra" design with an actual device under test. In this case I used a 25LC020A SPI EEPROM that was already on a breadboard. Getting the loops and statemachines figured out was the most time intensive part of the "Ultra" firmware so far, at least for me. Now that we have a working framework, I think things will progress really fast from this point.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 26, 2019, 01:13:34 pm
X

Couple updates to the firmware:
*SPI "r" command working
*Flipped LCD 180 degrees so we are pushing characters from left to right, instead of backwards
*Mode labels are written on mode changes (requires a full screen refresh which is annoyingly slow) this should be updated to use DMA
*Cleaned up LCD drawing functions
*Increased all SPI speeds to maximum
*Updated Bus Terminal logic analyzer with same color codes as the bus pirate ultra pinout

Todo:
*Use file system to load FPGA and LCD between modes
*Test I2C peripheral
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on October 27, 2019, 11:24:11 am
As much as possible, we'd like to move control of hardware to the FPGA so that everything can be controlled from the state machine command pipeline. In v1c we moved the voltage measurement to the FPGA by adding an SPI ADC. In a future revision it would make sense to move a few other things to the FPGA:


For debugging and self-testing we need to keep some redundant connections to the MCU as well, but primary control should be through the FPGA.

I had a look at replacing the DAC in the MCU with a small SPI DAC. Here's what I found:

MCP4902 8bit dual DAC TSSOP14
X
MCP4902 (https://www.microchip.com/wwwproducts/en/MCP4902) seems to be a classic Microchip part, available at Mouser for $0.99 in 100s (https://www2.mouser.com/ProductDetail/Microchip-Technology/MCP4902-E-ST?qs=sGAEpiMZZMswix2y39yldX1d8KpQmwEZWEysvlbA%2FfM%3D). However, the smallest package size is TSSOP14, and a quick check of SZLCSC (https://item.szlcsc.com/163537.html) shows they only have the SOIC version with 17 pieces in stock. That's not a great sign.
X
Each update of a DAC takes 16bits, maximum speed is 20MHz.

MCP48FVB02 8bit dual DAC MSOP10

X

MCP48FVB02 (https://www.microchip.com/wwwproducts/en/MCP48FVB02#datasheet-toggle) appears to be a part Microchip acquired when they bought Micrel. It comes in an MSOP10 package which is minor improvement over the MCP4902. It's a bit cheaper at $0.90 for 100pcs (https://www2.mouser.com/ProductDetail/Microchip-Technology/MCP48FVB02T-E-UN?qs=sGAEpiMZZMswix2y39yldfb5%2FLk%2F%2FQV6h%252Bh290m7Ahw%3D) at Mouser. It's not stocked at SZLCSZ (https://so.szlcsc.com/global.html?k=MCP48FVB02), which is a huge warning sign. Microchip Direct is really good about delivering parts in China if need be, but they can only deliver 1200 today (https://www.microchipdirect.com/product/MCP48FVB02) and new stock won't be available until February (three and a half months away).

X

It uses a 24bit command, which is a full byte longer than the MCP4092. Both the MCP4092 and MCP48FVB02 operate at maximum write speeds of 20MHz, so the MCP4092 will have a significantly higher maximum update speed.

DAC082S085CIMM/DAC084S085CIMM 8bit dual/quad DAC MSOP10
X

Here's where it gets a bit interesting. DAC082S085CIMM (https://www.ti.com/store/ti/en/p/product/?p=DAC082S085CIMM%2FNOPB) is a dual 8 bit DAC from Texas Instruments, available for $1.24 in 100s (https://www2.mouser.com/ProductDetail/Texas-Instruments/DAC082S085CIMM-NOPB?qs=7X5t%252BdzoRHCwdYFD1T00dg%3D%3D) at Mouser. SZLCSC only has 8 in stock (https://item.szlcsc.com/49736.html) for around $2 in 100s (13.20RMB). Low stock is bad news, and a higher RMB price than USD price that points to a limited stock or specialty chip to avoid (eg not something with high demand in China).

However, the DAC084S085CIMM (https://www.ti.com/store/ti/en/p/product/?p=DAC084S085CIMM%2FNOPB) is similar but has 4 DACs. We could use the extra DACs to add more programmable output power supplies, or a simple analog signal generator on a few of the IO pins. It's available at Mouser for $1.58 in 100s (https://www2.mouser.com/ProductDetail/Texas-Instruments/DAC084S085CIMM-NOPB?qs=7X5t%252BdzoRHD1%2FOyJvNSS2g%3D%3D), and at SZLCSC for $1.15 (https://item.szlcsc.com/151649.html) (8.68RMB) with 1700 available and 1300 shipped in the last month. That's several good signs: it's cheaper than the 2 DAC version ($2 vs $1.15), RMB price is cheaper than USD price, and there is a fair amount of stock and turnover at SZLCSC which means it's actually being used in production. This seems like a good candidate. Just to further verify, there are 50K in stock at the TI store, and 20K in stock at Digikey (https://www.digikey.com/product-detail/en/texas-instruments/DAC084S085CIMM-NOPB/DAC084S085CIMM-NOPBCT-ND/1206424) for a slightly higher price.

X

The update command is 16bits, but where it really shines is the 40MHz maximum update speed (twice as fast as the Microchip DACs).




Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on November 01, 2019, 04:45:24 pm
X

2 inch display carrier board for Ultra v1d:
*Uses 10 pin 0.5mm flexible PCB connector, wired to the main board with a 1:N connection. This connector is much smaller and thinner than the 1.25mm connector on v1b, it reduces the space needed between the display board and the main board.
*Flipped LCD orientation 180 degrees so font data can be written into bounding boxes in a more natural “left-to-right” orientation, eliminating the need to precalculate the text end point and write characters in reverse sequence
*Nudged the display towards the IO header. We’ll experiment with some buttons in the remaining available space
*Decoupling capacitors on LCD power pins

X
2.8 inch display carrier board for Ultra v1d (in progress, todo:)
*Add decoupling caps to power pins
*Add slot for display flexible PCB cable to reach the connector on the back
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ferdinandk on November 02, 2019, 01:07:38 pm
Very neat project so far, looks like it will be able to compete with Saleae's Logic Pro series.

Regarding the ADC and DAC: have you thought about implementing those in the FPGA? There is a white paper about implementing and ADC in one of their FPGA's from Lattice [1]. The DAC can be as simple as a PWM with an RC filter.

[1]: https://www.latticesemi.com/-/media/LatticeSemi/Documents/WhitePapers/AG/CreatingAnADCUsingFPGAResources.ashx?document_id=36525
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on November 02, 2019, 04:01:00 pm
Very cool, thank you for the link. I will have to try both methods suggested in the app note just to be more familiar with the internals of the ADC.

The ADC speeds (15 and 50khz) are very low though. With the TI ADCs we can do 1msps or 2.5msps which is in DSO nano territory. Eventually we'll do a dual rail parallel ADC at 100msps, but not till we move to the bigger BGA FPGA chip.

The DAC side would be really easy with FPGA pin, agree. Since we're using two in the power supply system I'm quite worried about the noise though. The other two I'd like to put behind a op amp with shutdown and output analog waveforms on two IO pins. Noise is still an issue with the DACs though because they have almost zero PSRR.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ferdinandk on November 02, 2019, 05:50:56 pm
The ADC speeds (15 and 50khz) are very low though. With the TI ADCs we can do 1msps or 2.5msps which is in DSO nano territory. Eventually we'll do a dual rail parallel ADC at 100msps, but not till we move to the bigger BGA FPGA chip.

The DAC side would be really easy with FPGA pin, agree. Since we're using two in the power supply system I'm quite worried about the noise though. The other two I'd like to put behind a op amp with shutdown and output analog waveforms on two IO pins. Noise is still an issue with the DACs though because they have almost zero PSRR.

True, the sample rate of the ADC is quite lousy. But hey, it's basically free  :D

If you're worried about the PSRR of the PWM DAC you can run them through a buffer (e.g. inverter gate) powered from a reference.

I'm aware that these solutions are a bit of an oddity, as a cost saving of 3 USD won't make a big dent in you total BOM cost.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on November 03, 2019, 10:38:41 am
The DAC datasheet also suggests powering from a shunt reference to reduce noise. I've been considering moving the ADC and DAC to a 3.0V reference. That reduces voltage measurement range to 0-6volts instead 0f 0-6.6, which makes a lot of sense and gives more resolution in the most likely to be used range (5.0V and under).
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on November 03, 2019, 11:17:49 am
Change List v1e:
*All PSU control to FPGA
*Flash chip to soic8_208 so we can use 128Mbit flash (https://www2.mouser.com/ProductDetail/Winbond/W25Q128JVSIQ-TR?qs=sGAEpiMZZMtI%252BQ06EiAoG4%252BhDIVn9lGKEu9OBgPZVXY%3D)
*Give some thought to replacing the 571/245 with something suitable to all the logic levels supported by the buffers (maybe something with two independent rails?)
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on November 06, 2019, 10:40:35 am
X
Received 100 Bus Pirate cables using our pinout colors from DirtyPCBs.com custom cable service. The cables were just over $1 each for quantity 100.
X
The primary reason we ordered these now is to get a feel for how the pinout color scheme works in practice before we commit to it permanently.
The leads are 30cm long, which seems a bit unwieldy in real life. The next version will be a few centimeters shorter.

The ends are terminated with 1 pin female "Dupont" connectors. These are easy to use with breakout boards and bread boards that have 2.54mm header pins. We'll need to choose a nice probe hook and mating crimp eventually.

X
While the wire quality is fine, it's a bit stiff and unpleasant to work with. We're still looking for the perfect wire. The Saleae Logic cable has really amazing tangle free wire with great flexibility. We took the Saleae cable to a bunch of wire manufacturers in Shenzhen, but none of them had anything close in terms of quality and flexibility. They did confirm that it is not silicon coated wire, so our search will continue.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ferdinandk on November 08, 2019, 05:57:24 pm
I have bought these jumper cables [1] from AliExpress and they are super nice and flexible. They are advertised as being made from silicone wire.

[1]: https://aliexpress.com/item/32811041093.html
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on November 09, 2019, 01:36:29 pm
Very nice. If you bend the wire really hard does it leave a crimp in the wire? I bought various samples of silicone insulated wire from the market in Shenzhen, and while it is a big improvement over PVC wire, they are all kind of "floppy" and easily left with a permanent crimp when bent 180 degrees.

Someone also suggested we look at multimeter probe wire and suppliers, which has been pretty promising as well. According to a few probe datasheets I've read, the wire is double insulated with silicone in two different colors so bends and abrasions are readily apparent.

Overall it feels like we are getting closer :)
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ferdinandk on November 11, 2019, 04:55:06 pm
Whether it leaves a kink in the wire depends on the radius of the bend. A radius greater than ~3 mm don't seem to do anything to the cable.

Besides the material of the insulation you also have to look out for wires with very fine strands. These tend to be much nicer and more flexible.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on November 22, 2019, 12:07:00 pm
X
We received the v1d PCB, stuffed it, and tested the new power supply features :) Going great so far!

Next we'll get the ADC (went 12 bit) going from the FPGA, and then add the display board with the bigger 2.8" LCD.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on November 27, 2019, 11:10:01 am
X

I've located a couple suppliers with silicone coated fine strand tinned wire that look promising. I'm getting samples in 20AWG (1.80mm OD) to have a look at the colors and quality.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on December 03, 2019, 03:25:03 pm
X

Reading the ADS4072 ADC using commands sent to the FPGA. This is great! Even with the really long delay I inserted for testing, the measurement is precisely timed. I don't see any of the extreme latency and delay that was cropping up when we paused the FPGA state machine to let the MCU take the analog measurement. Can't wait to get the DAC connected to the FPGA too.

Here's some build notes:
*R900 wrong size ()
*R15 wrong size (1210)
*many 0603 0.1uf/1uf->0402
*2 R on back current shut ddown are 0603->0402
*U101 to 208mil (128mbit flash)
*R908/910 -> 100K
*changed 909,911,912 to 1K
*C306 shoud be 0402
*According to Twitter, vcc and ground should be separated on the flex connector to avoid shorts when it moves

*add mcu ADC connection to cs, other minor changes to cs outlined in the updated schematic
*We need to replace (try) the 245/573 with 4 x 74lvc2t45s
*LED anode and cathode are reversed on the 2.8" LCD connector
*200R protection resistors from FPGA to driver nt45 ICs.
*Pull down on the MUX and 245 enable/direction pins

Things to think about:
*3volt analog reference
*move remaining control to FPGA
*Maybe remove the open drain drivers if we end up with 4x 2T45s (and associated pull-X resistors on direction pins)
*2 x 4051 instead of 4067 (cost, supply issues)
*Choose proper diodes for the op amp protection
*VREG LED and VREG status detection
*What to do with USB LED?

Things to test on this version:
*back current protection using the new ADC connections
*probe all points of the PSU
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on December 06, 2019, 12:29:26 pm
XX We identified four factories selling highly flexible silicone coated wire with fine tinned copper stands. The smallest (common) strand size for Chinese factories seems to be 0.08mm, with 60 strands in a 22AWG wire. The first set of samples arrived this week, three more should be here next week.

The only issue seems to be purple, not much out there in purple. Also, if we want the hip unprinted wire its going to take a fairly massive MOQ. If we end up customizing the wire, at least we have the chance to get the exact colors we want.

The screenshot is from a WeChat sight that Jam and Abin sent from the Shenzhen office :) It looks really flexible and kink-free.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: Sjaak on December 11, 2019, 08:24:50 pm
Tried today to come up with some code I accidently bricked my buspirate.

Tried to port the bootloader to board 1b. The only way I think it is possible is to short swdio and swdclk as no other pins are directly exposed on the currents versions. In order to use these pins you need to disable SWD (and JTAG). Due to an error i permanently disabled it. For production version we need either a button or solderable jumper or expose the boot0 pin and an UART. I prefer the boot0 and UART option as it provides an extra option to load programs on the BusPirate.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on December 12, 2019, 02:11:46 pm
Are there any fault indicator bits that survive a crash/stack overflow? I thought maybe we could use that and a watch dog timer to reset into bootloader if anything goes wrong. The pic has a persistent bit that survives a reset in addition to the stack overflow bit. If there is something similar we can combine them to enter the bootloader without external pin.

however I agree an external pin is needed for worst case scenarios.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on December 12, 2019, 02:34:14 pm
X

The HDL (https://github.com/DangerousPrototypes/BusPirateUltraHDL/tree/command-data-refactor) is complete enough to start testing on real hardware. This update puts almost every feature under control of the state machine in the FPGA so commands can be pipelined with repeatable precision. Commands (http://dangerousprototypes.com/forum/index.php?topic=10364.msg70426#msg70426) (write/read SPI, set/clear pin, measure voltage, update PWM, enable pull-up resistors, etc) are pushed into a FIFO buffer using a 17bit command/data protocol inspired by the interface of ST7789-based LCDs. When the state machine is enabled the commands are processed in one continuous stream.

Verilog HDL for the FPGA is on github, the latest updates are currently on the command-data-refactor (https://github.com/DangerousPrototypes/BusPirateUltraHDL/tree/command-data-refactor) branch. A synthesized version of the bitstream is attached below.

@giggiu16 has already build his own v1d. I have a few more boards if you want one. PM me.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: Sjaak on December 12, 2019, 09:52:00 pm
Are there any fault indicator bits that survive a crash/stack overflow? I thought maybe we could use that and a watch dog timer to reset into bootloader if anything goes wrong. The pic has a persistent bit that survives a reset in addition to the stack overflow bit. If there is something similar we can combine them to enter the bootloader without external pin.

however I agree an external pin is needed for worst case scenarios.

Easiest way would be an extra pin. To make it safe don't use the jtag pins as I tried. The use of the builtin serial bootloader would enable restoring the bootloader and firmware to most people (I'm assuming 90% people would have an USB to serial convertor handy). That needs to break out boot0 and a serial port. Since we moved to 4 layer we have some more room to route signals :D

Regarding resetcauses a quick google gave me: https://stackoverflow.com/questions/34196663/stm32-how-to-get-last-reset-status

currently (i used the bootloader from the NG version to start) if you write 0xB007 to BKP_DR1 register it enables the bootloader after a reset. These registers are battery backed up register and holds data during resets (as long as the device is battery powered)
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on December 30, 2019, 11:34:53 am
X
It's been a bit quiet here, but we've nearly completed debugging of v1d. v1e is routed and we'll make a small batch of them (10?) soon, but probably after spring festival.

This is the prototype display board for v1e:
*2.8" IPS LCD with capacitive touch display. The capacitive touch sensor is I2C based, so we added an I2C bus and interrupt pin to the flex connector
*2 silicone buttons with RGB LEDs under each. The buttons are controlled through a TCA9534 I2C IO expander, basically a 5volt tolerant PCF8574 at half the price. The TCA9534 uses the same I2C bus as the capacitive touch sensor, and gets a dedicated interrupt signal on the flex connector
*6 additional IOs (routing in progress) from the unused pins of the TCA9534
*RGB LEDs (SK9822) share an SPI bus with the LCD. The SK9822 runs at 5volts and uses a two pin protocol that can be driven by an SPI peripheral, but it doesn't have a chip select pin so it can't share an SPI bus with other peripherals. We use a 74HCT573 as a level converter (3.3->5volts), and the 573's latch pin as a pseudo chip select
*The board is now powered from VUSB (5volts) and has a 3.3volt regulator

X

The schematic is nearly finalized:
*MISO on SPI should be jumpered. This leaves a disconnected pin between VUSB (5volts) and the 3.3volt logic pins
*Route unused IO pins to a header
*Run LCD backlight from VUSB
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on December 30, 2019, 11:50:32 am
X

This is a really high quality display from Startek. It's quite expensive. We're going to try a few other compatible displays. I'll have several other screens to test tomorrow, as well as our probe cable sample materials and other goodies.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: mikestefoy on December 31, 2019, 08:35:22 am
I am very impressed with your progress, and competence.

I am itching to get my hands on a working unit.

what is the model number of the 2.8" Startek LCD.

I like the bigger 4.3" one

https://www.alibaba.com/product-detail/4-3-inch-480-800-capacitive_60679375169.html?spm=a2700.details.maylikever.12.132f19589jYDSj

Mike
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on December 31, 2019, 10:19:00 am
Hey Mike,

That's a nice display. Anything over 320*240 generally needs a 8 or 16 bit parallel interface (we use SPI). I imagine in v2 eventually we end up with a second stm32 as a graphics driver or a big mcu with MIPI.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: mikestefoy on December 31, 2019, 02:47:41 pm
seems to imply its SPI also, inteface says IIC, whic in chinglese means SPI

the    ILI9806E seems to support SPI

whats the model of the 2.8" one you are looking at ?

Mike
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on January 02, 2020, 12:44:48 pm
Currently I'm using KD028QVFMA017 (https://www.alibaba.com/product-detail/2-8-inch-240-320-ST7789V_60805335168.html?spm=a2700.7735675.normalList.8.31e411f5OK0acf), for capacitive touch we're using KD028QVFMA017-C002A (https://www.alibaba.com/product-detail/2-8-inch-240-320-ST7789V_60799944075.html?spm=a2700.7724838.0.0.6fa93f2cDyoX56&bypass=true).

Startek's website is down, but when it comes back up the 4.3" datasheet is here (http://www.startek-lcd.com/res/starteklcd/pdres/201801/20180106171904908.pdf) and I'll have a look.

In general driving all those 16bit pixels from SPI seems slow. We have room for improvement using DMA to transfer the background images from the flash chip to the display, but i have this nagging feeling that we'll need to use an 8 or 16bit parallel interface  when we get to a future v2 or v3.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: Sjaak on January 10, 2020, 11:40:01 am
Most displays can be updated partially, which makes the impact smaller. The only things changing (frequently) are the voltages which occupies only small areas.

general workflow for the v1 I suggest:

display off, send the big gfx using DMA, display off and partially update the voltages during use.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on January 10, 2020, 01:54:07 pm
X

For the bigger display - SPI interface pins are listed in the pin description, but there are no IM0...3 pins to select the mode (maybe this chip works differently). The schematic also doesn't mention an SPI mode. I have not looked at the ILI9806E datasheet, maybe the mode is selected differently than the smaller version.
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: mikestefoy on January 12, 2020, 01:39:48 pm
The data sheet says

a-Si TFT LCD Single Chip Driver   480(RGB)x864 Resolution and 16.7M-color The ILI9806E is a 16.7M single-chip SOC driver for a-Si TFT liquid crystal display panels with a resolution up to 480(RGB)x864. The ILI9806E is comprised of a 1441-channel source driver, an gate-IC-less level shifter, and a power supply circuit.   The  ILI9806E  supports  3-line  serial  peripheral  interface  to  input  commands.  The  ILI9806E  supports  a  RGB  (16-/18-/24-bit) data bus for video image display. For high-speed serial interface, the MIPI DSI interface mode, the  ILI9806E  supports  two  data  lanes  and  one  clock  lane  for  high-speed  and  low  power  transmission  in  both  directions with low EMI .

no idea what a MIPI DSI interface is, but an FPGA should eat it !!!

seems to imply a 10 pin interface see datasheet page 20.

needs  SPI to set register IM[3:0] to 0111  or 1111, then its activated, with data on HS_D0P,HS_D0N, HS_D1P, HS_D1N, HS_CP, HS_CN, SDI,SDO,SCL(rising or falling edge) ,CSX
Title: Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Post by: ian on January 13, 2020, 06:17:15 pm
Interesting. Commands through spi and pixel data parallel. MIPI is the way to go. V2 will use an arm with MIPI support.