pic have access to the spi eprom iirc so in theory there could be a change done to the firmware to read a "id string" from the eprom and return it. Now the question is, is it possible to embed some type of "id string" in the bitstream as from what I figured how this fpga's without non volatile ram work, they just slurp the data from spi eprom and configure themselves, so adding such string would probably mess up the fpga - or is there a "comment" field in the bitstream that could be used?
(I figured that it is impossible to do it "now" - checked out the source for both firmware and bitstream, but I think it would be very cool add on .. but if Jack Gassett manages to make this new approach works - auto memory depth extension when you select less bits to log, it might not be needed)
[quote author="liyin"] For those that don't know, RepRap uses Polycaprolactone, which is also known as Polymorph, Friendly Plastic, or Shapelock. So you can still do stuff even if you don't have a 3D printer. [/quote]
no actually, in most cases it does not. it can use it but it is avoided as you cannot make a complex shapes with it, you can't span any gaps and it's thermal spec's are pretty far from ideal with regards to 3d printing (it cools too slow so you have to print tooooo slow in order not to produce a gue of plastic). it uses ABS or PLA.
PCL (polymorph/shapelock) loses the shape on pretty low temperatures (60-70C iirc way low for heating parts like xilinx fpga) and ABS is extruded at 240-260C and PLA on 210-220C .. so way above the temperatures pcb will produce ... shapelock is cool stuff for hand molding at low temperatures.
I don't see that there's any indication in protocol how can one query OBLS for it's "capabilities / specs". For e.g. I pushed 24k8bit bitstream (is that the proper name for the fpga "firmware" ? I just started working with fpga's last week so new at this) to the eprom, is there a way for client to query OBLS for "available channels, available memory, available scan rate" ?
I designed a simple strap on protection for logic sniffer that protects the underside of it from the nuts & bolts & solder drops & other conductive stuff on your table. If you have a 3d printer attached is the stl file, it prints easy.
pgc+pgd+reset did the bootloader trick, then it has the pid as in the batch (the bootloder is a hid one, not a cdc) - so this works nicely bootloader on board is 0.2.2 (possibly the latest one)
and the java client (original one) connects but only from 32bit windoze, was not able to make it work from 64bit windoze / linux .. will try later to check out rxtx maybe it's 32bit only ..
thanks for help, this is going to get some getting used to but looks like great tool
EDIT: removed and reinstalled CDC driver and it works properly on 64bit windoze, will check linux bit later but with regards to device it woks awesome I already managed to solve the problem because of what the device was purchased
OBLS just arrived and looks like I too have this problem - vid this device answered as is 0x000A (not 0x04D8 as all the scripts suggest) - it is serial device, but when I try to connect using terminal - I get no answer from the device - when I reset device the PWR led go on, ACT flash few times and then go off and TRIG led go on - nothing on the terminal - board states v1.01, crystal near pic is 16MHz - when I hold the update button and press reset, both pwr and act led's go on and device don't register (USB stays silent)
I can't say there's no firmware in the pic as if there is non the usb would of staid silent, but it seems there's "wrong" one in and there's no bootloader in .. I have pickit2/pickit3/buspirate so any of them should be able to burn the firmware in - should I proceed and burn the bootloader in, I assume OpenBench_LogicSniffer_2.1bootloaderOLSv1-bootloader-v2-16MHz.hex is the proper bootloader?
[quote author="ian"] the Bus Pirate supports the open source OpenOCD JTAG debugger from the binary interface mode: http://openocd.berlios.de/web/ [/quote]
ah, so openocd bit bang's it, thanks for the explanation.
Did you use the low-level JTAG user mode library? We're trying to give it an update - what features have you used in the past, and how could it be tweaked to work best for the things you do?
Nope, I just tried it to see if it works.. have not used it at all. Just started to work with some cpld's (cold runner2) and fpga's (spartan 3an) so not too experienced with the whole jtag chain thingy but looks like I will have to use it more and more so BP might be useful in that regard
I am confused so if someone can shed some light ... tnt made few patches regarding jtag, ian made a nightly build - but there's no jtag mode on the 5.2 firmware at all ?! What one need to do to make jtag mode work ? (except fall back to 4.x)