[quote author="dogsbody"]A normal capture 4-bit mode is possible, with a simple 4bit->8bit data accumulator. A 3-bit rle-encoded mode could also be done. It would require client support however for both normal & rle modes.
Benjamin, have you tried using the 8-bit rle mode? Your ols only stores data on change, and it can really amplify the capture window. -- IED[/quote]
Yes i have tested the 8bit + RLE and it's very good, it was a question to have even longer trace to analyze complex protocols with lot of samples and of course such needs are for slow speed like 1 to 8Mhz.
Now the OLS is pratically perfect thank you all for this amazing project.
But i think about a 4 channels mode in order to acquire more samples. I think it will be perfect for Serial, SPI, I2C and other signals which require 4 or less channels with the huge benefit to have 2 times more samples than 8chan mode.
An other very interesting feature will be to have 4 or 8 channels live capture for unlimited number of samples depending on PC memory like the Saleae Logic Analyzer, which is very interesting for long run studies on special devices/protocol.
[quote author="jawi"][quote author="TitanMKD"]I'm just testing latest FPGA (ols_verilog_meta4.zip) & PIC Firmware (ols.firmware.v2.5.zip) with OLS 0.9.3. My configuration is Number scheme = Test Mode. All seems good except 200MHz mode which often fail and stop sometimes at 50% (tested with channel groups 0 only and Recording size automatic maximum). The problem is after that failure OLS cannot capture anything even when changing to 10, 20, 100MHz ... and i need to restart OLS and it work again. I also quoted the only way to have 200MHz working a bit is when 2 channels (group 0 & 1) are quoted together with Recording size = 6Kb all other configuration like group 0 only or Recording Automatic size fail with an error or in best case captured data are totaly wrong like in screen capture below. I will do more test to quote all cases working and non working at 200MHz In my example i only attached buffered channel 0,1 & 2 to unbuffered channel 5,6,7 other channels are connected to GND.[/quote]
I'm not sure if and whether the 200MHz mode works with the Verilog version made by IED/dogsbody. Does it work with the 2.12 release (unless you've upgraded to the latest PIC firmware)? I've never really given it a test, but maybe somebody else on this forum has experience with it?[/quote]
I do not remember if it worked on v2.12 and IIRC it was very instable. Anyway now the latest version is the most stable even if 200MHz is not really working and now RLE is really working correctly !!
I'm just testing latest FPGA (ols_verilog_meta4.zip) & PIC Firmware (ols.firmware.v2.5.zip) with OLS 0.9.3. My configuration is Number scheme = Test Mode. All seems good except 200MHz mode which often fail and stop sometimes at 50% (tested with channel groups 0 only and Recording size automatic maximum). The problem is after that failure OLS cannot capture anything even when changing to 10, 20, 100MHz ... and i need to restart OLS and it work again. I also quoted the only way to have 200MHz working a bit is when 2 channels (group 0 & 1) are quoted together with Recording size = 6Kb all other configuration like group 0 only or Recording Automatic size fail with an error or in best case captured data are totaly wrong like in screen capture below. I will do more test to quote all cases working and non working at 200MHz In my example i only attached buffered channel 0,1 & 2 to unbuffered channel 5,6,7 other channels are connected to GND.
Just a good hint for guys with problems on USB installation a good tool http://www.nirsoft.net/utils/usbdeview.zip is avalailable to see all driver installed to disable/enable or uninstall them. It could be also very useful to cleanup/uninstall unused old USB device registered ...
[quote author="sburlappp"] Please excuse me if this isn't the right place for this, but it's a newterm feature request, and this is the newterm thread....
I'm trying to troubleshoot a serial device which I believe is running a little slow, so its 2400bps is more like 2300, and the BP is picking up the start bit as a data bit and throwing off the data capture. Would you consider adding support for arbitrary UART bitrates? Maybe by changing the "10. 31250 (MIDI)" setting to "custom" and providing a "change speed" command, maybe even a speed detect macro? [/quote]
I will advise you to use BP in SUMP mode using Sump's Logic Analyzer Client to have exact time.
I have done some test with PWM on latest Firmware v5.0 (Firmware v5.0-pre3 (r358) Bootloader v4.2) with my Bus Pirate v3b and my Open Bench Logic Sniffer.
It seems there's a problem for PWM Duty Cycle at 1% output signal is always set to low state !! (it works for Duty Cycle99%) See the other test it seems some PWM Duty Cycle are not very accurate depending on test.
For information and fun i can also run the BusPirate Firmware (your .hex version with easter egg and no symbol ...) using Simulator with the following hint (to avoid reset due to flash access): SIMU main() -> Goto 0xA1E0 -> Set BP to 0x804E -> Run -> Set PC to 0x8050 -> Run And it display things in virtual com ;-) It can also be simulated ...
I have just uploaded your new version and i was testing it basically using PirateShip GUI on Windows and it appears some command like "V" are not recognized anymore (reply Syntax error at char 1) and require "v" because automatic conversion between Lower<->Upper case seems not enabled anymore.
I have also tried to build it myself (without changing any file) using MPLAB IDE (v8.50) in addition to MPLAB C30 (v3_23 -> pic30-gcc.exe -dumpversion return 4.0.3) to build C code. It happens your hex and map is different than mine built using latest source in SVN (the-bus-piratetrunksourcenewterm from http://the-bus-pirate.googlecode.com/sv ... ce/newterm). For information it seems i have exactly same version as yours in base.h -> #define BP_FIRMWARE_STRING "Firmware v5.0-pre2 (r356)". And for information my build can't be loaded by pirate-loader.exe it say there's a checksum error in the file but it work fine with yours.
I have just received my OLS v1.01 from Seed Studio and it seems all work fine (at least using Test Mode and with some previous test using BusPirate+PWM) !!!
I have logged everything in Test Mode (configuration HW/SW used ...) in the attached zip file (containing OpenOffice .odt full description).
[quote author="ian"] Hi Titan - The 32 chips are really interesting. Unfortunately, they lack PPS (peripheral pin select), the key feature that lets us move all the different hardware peripherals to the same 5 output pins. [/quote]
I think PPS feature can be done by software abstraction layer (define or function) easily. My idea about a new Bus Pirate HW is not really to keep compatibility with old one PIC24 which are very far to PIC32 in power/functionality (frequency, memory, IO, Ethernet/USB speed ...).
PS: I have forgotten to introduce me, i'm software engineer in embedded critical software (from low level to OS stuff) since lot of years. I'm ready to help (design/code and tests) such project to have very optimized code using fast mechanism like DMA/Interrupt stuff on advanced µC like PIC32.
The Bus Pirate is very good but i have idea to use a faster PIC(PIC32 with DMA and lot of ram/flash/speed...) for next version of Bus Pirate V4 ? The idea will be to use PIC32MX695F512H full spec here:http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en545654
Max Frequency is 80Mhz (and can be overclocked to more than 100Mhz) and DMA feature is really interesting to obtain for example very fast input capture (for logic analyzer) using DMA channel and other funny stuff, in addition to USB and Ethernet10/100Mb for very fast upload/download (to SUMP or PC) stuff and all using only DMA. The price PIC32MX695F512H is only about to 7euros/10US$ and we could have a very good Bus Pirate for maybe 50US$.
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