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Messages - DavidFrancis

17
Client software / Re: Jawi's Logic Sniffer client software - releases and requ
I have made some more mods to the RLE decode routine to make it more compatible with dogbody's v4 bitstream. I have added code to handle the situation where non contiguous channel groups are selected.
I will now work with say groups 0 and 3 selected. I will also work with rasmus v7 bitstream but the trigger point indicator may not be accurate. I have attached code of the modified routine for you to test.
20
Open Bench Logic Sniffer / Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi
I have been testing dogsbody's ols_verilog_meta2 bitstream and finds that it handles rle counter rollover slightly differently to the other bitstreams. the others  outputs a data word between count rollovers whereas this one does not. This is not handled correctly in Jawi client as all counts except the last  are ignored . This is more noticeable at 8 bit captures as rollover occurs more frequently. I think this new bitstream is this best way though as it allows slightly more samples.
I also found the 24 bit rle to does not output the counter correctly in that it outputs the most significant byte as all zeros so it does not show as a count.
I think this great work and I look forward to testing the advanced trigger option.
21
Open Bench Logic Sniffer / Re: Status of RLE
Further to my previous post I have now carried out further test on the RLE and I have found the 'capture aborted' is most likely caused by old data in the ram when trigger mode is set with pre capture and not enough events to populate it.
I think the a similar problem gives incorrect readings on a first scan after memory depth has changed. I found it best to do a non RLE scan first after a memory depth change to set the memory to compatible values.
Other than these problems RLE  works well at all memory depths. If the timer is made configurable the it would be very useful.
22
Open Bench Logic Sniffer / Re: Status of RLE
I have tested the new_rle_0.02 bitstream from RASMUS. I seams to  handle 32 bit overflow correctly.
On free run with no inputs  32 bit capture and rle set  the client returns from capture in about 100 sec with 4 full rollovers and a partial count which I worked out to be a total of 104.2 seconds. I got these values from a small C# program which just outputs the basic  setup info and logs the raw returned data.
I then tested using a pic chip which outputs a 23 khz clock with a period of interruption of 50 sec. (2 cycles 50 sec of zero and the 1000 more cycles)
I find I get capture aborted on repeat captures with trigger set. The first capture  after  reset works ok. This is seems to happen if the previous capture had a rollover.
This does not happen with 2.12.
I will continue testing with other conditions.
23
Open Bench Logic Sniffer / Re: Status of RLE
[quote author="rasmus"]
All right, I've implemented a few things that could use some testing:

32-bit (31-channel) RLE works as before.
16-bit (15-channel) RLE works (I think) but the client doesn't support it yet. You'll see the raw RLE data in the client.
8-bit (7-channel) RLE works with the same caveats.

All RLE modes time out and go into normal sampling mode after 20 seconds if the memory isn't full by then.

Known bugs:
RLE does not work reliably with sample rates below 10 kHz because of how the timeout works.
The first run after changing either channel groups or sample rate does not yield reliable data.
[/quote]
I have tested your new bitstream. This is a good improvement but I think the timer is only necessary for the 32 bit capture.
At 16 bit capture the total capture time is only a little over 3 sec at 100Mhz assuming 15 bit counter.
Your timer of 20sec is to short to fully test the 32 bit capture as a rollover of the counter takes just over 21 sec.
I did notice that bitstream 2.12 did not show the correct rollpver count. It showed Bfffffff and not ffffffff. Have you corrected this?
24
Client software / Re: Jawi's Logic Sniffer client software - support and bug reports
I have been looking at the RLE mode and have made changes to LogicSnifferDevice.java which I think improve the trigger position indicator and handling of counter overruns. I attach my modified file for your consideration. I have tested it on my system with bitstream 2.12 dynamic depth. RLE only on 32bit captures. I have been able to capture over a 50sec of events at 100Mhz with the timing looking accurate. I have difficulty generating a 50s timing with 10ns resolution .
I did notice the display doing not always working correctly at high zooms possibly a  rounding error in the display routine.
25
Open Bench Logic Sniffer / Re: Status of RLE
I ran you test bitstream and all ran 100% successful 20 attempts at each setting with RLE and Noise Filter selected.
I had to drop the sample frequency to 50MHz for the Test mode as the client had heap overflow.
The inside mode had a 6.104 kHz 50% sample on pin 0
The outside mode had a 3.052 kHz 50% on pin 0
The Test mode had a 1.526 kHz 50% sample on pin 0
these are as indicated by the measure tool .
This test was on a Windows 7 64bit machine.
I must say the the only problem I have ever had with the RLE mode is the heap overflow in the client.
I have used it extensively to debug a parallel  port interface using all 16 buffered inputs with great success.
26
Open Bench Logic Sniffer / Re: Status of RLE
Putting resistors on the FPGA inputs will only work for the unbuffered inputs.  On the buffered inputs the buffer output will override these resistors.
I have found connecting unterminated probe leads to the buffer inputs is the source of random noise which upsets captures using RLE. I now either use single female to female leads to connect only the required pin to the circuit under test or earth all unused probes. This is easily done by clipping all unused probes to a short length of earthed  fuse wire. It is also worth keeping the OLS board away from sources of interference.
27
Open Bench Logic Sniffer / Re: Status of RLE
I seems the trigger indicator problem only occurs when RLE is selected and shows up when there is a regular clock input.
Attached png shows trace 500khz ols clock aux clock 10khz on pin 0 trigger pulse on pin 1 set for 10% before.
28
Open Bench Logic Sniffer / Re: Status of RLE
I have being doing some test of the OLS using  RLE. I have bitstream 2.12 runing on a Windows 7 machine using ols-0.9.1 32 bit capture and have the following comments:-

1 The total capture time is limited by the java client to about 15 million clock periods. After that the client crashes with heap overflow. The number of samples selected does not affect this.
2 The trigger indicator is shown incorrectly. If a 25/75 pretrigger is selected the trigger event is shown at the correct 25% position but the indicator and zero position is shown at 75%.

 Using a 10Mhz clock 1.5 seconds can be captured if a 1khz aux clock is added to an unused input and the signal does not have many transitions.
29
Open Bench Logic Sniffer / Re: My experiences with the OLS
I have been testing the SPI v2.04 and find it about 10 times faster than the UART version, that is about 1000000 baud.
Because there is no UART the baud rate is not used, the speed is set by the the speed of the  SPI  and  USB interfaces.
I have not been able to get the 16 bit by 8k mode to work. When I set groups 2 an 3 off and select 8k all I get is the first 4k repeated.
The RLE mode it seems to be limited to a max of approx 16 million clock periods. I suspect this is in the java client.
Any recording which exceeds this causes the java client to hang until the close button is pressed.

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