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Messages - alexwhittemore

4
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
No, actually you are more right than I thought, I hadn't realized the core used direct runtime LUT modification. But the point remains that the mechanics of trigger string to LUT config compilation remain to be worked out, and there's no guarantee that more advanced triggers can fit into just the LUTs currently allotted.

Anyway more advanced triggers as you suggest would be a real boon anyway, so a more serious FPGA developer than I should look into it in more depth.
5
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
It doesn't *seem* very complex, but that doesn't mean it isn't.

Those kinds of triggers aren't difficult for a generic processor to handle, but the issue is (as you seem to be aware) translating it to FPGA hardware. Yes, you could write a parser that boiled a given expression down to verilog, but even if you did (which isn't trivial as it seems), you'd still have to flash a new FPGA bitstream every time you changed the trigger, which is a bit silly. Without automated tools, it'd look like design trigger>open xilinx ISE>implement HDL>synthesize>place+route>flash>use. You can imagine that, even if you automated those steps, it's not like it'd be as quick as change trigger>restart capture.

Of course, you could implement some kind of generic logic in the FPGA to handle complex triggers, then simply *configure* that logic at runtime when you make a complex trigger, in much the same way demon core + Jawi's OLS client do now, but the resources on the 250k gate Spartan 3E are already pretty much maxed. And it took talent even to get there.

The problem boils down to: every trigger statement you can think of has to be evaluated for every sample taken by the OLS, meaning it has to not only be done in combinational logic (and not some kind of post processing), but it also has to meet the timing requirements for the given speed you're operating at (which can be up to 200MSPS for 4ch, I think).

Not to say it's impossible by any stretch. But it's not EASY, and it might be impossible given the current limitation of 250k gate Spartan 3E hardware in production now.

Now, I've also been away from this project for quite a while, so perhaps there have been some changes I'm not aware of. But it looks like the current sparkfun OLS is still using the same xilinx part, so I don't think I'm too out of date on this answer.

Brutal thread resurrection, by the way.
6
Client software / Re: Jawi's Logic Sniffer client software - releases
[quote author="jawi"]
Odd. The DMG opens just fine on my machine. I'm still on Lion, though. One thing I saw was that Chome mentions it downloaded it from dangerousprototypes.com? Did you try to download it from my site, ols.lxtreme.nl?[/quote]

Yeah, you've uploaded the same actual thing to both places, so trying both now, they do the same thing. The fact that it mentions being downloaded by chrome from here is a function of the new Gatekeeper system. Which, incidentally, causes newly downloaded unverified apps not to run. But that's not what's happening here. I'd be surprised if you had to recompile USING a ML system, though, that seems a bit silly.

EDIT: Huh, this is totally peculiar. ML's Gatekeeper says if something is newly downloaded, allow it to run based on your security preferences, which can be "run only app store apps," "run app store apps and those from trusted developers," or "run any apps." The default is the second, which you'd think is unacceptable, but on a one-off basis, you can actually run any app by simply right clicking and selecting open - it overrides the setting. In any event, the dialog box you get when trying to run a non-trusted app the first time is NOT the one I posted above.

BUT, some people are saying that error magically goes away if you set the above option to "allow any app." So I did, and now magically, it launches no problem. See http://forum.vuze.com/thread.jspa?messageID=265089. Weird.

Indidentally, I get the attached java error trying to launch the app from the .DMG, but then running apps from the .dmg is very often bad, so that's no surprise.
8
General discussion / Re: Just put my personal eagle library on github
I really like the idea of a consolidated library, someone (ian :) just needs to say 'here we go, contribute!' The scripts thing might be interesting from the standpoint of version control for individual parts-at-a-time rather than having to commit and stomp on a whole new library every time you edit a part (which would be hell for merging changes from multiple people).
9
USB Infrared Toy / Re: IR Toy v3 BOM
I know nothing about PIC programming whatsoever, and don't have a programmer, so that's out :). Let me know if you get anywhere, though, so I can build my board :)
11
USB Infrared Toy / Re: IR Toy v3 BOM
If I stuff the board with the v2's 18F2550, and the same IR components, is there anything substantially different that the software won't work?
12
General discussion / Re: Possible Eagle license giveaway? You decide.
Re: need vs want schematic sheets: in terms of getting a board designed, fabbed and stuffed, you're right, you just don't need multiple sheets. However, I HAVE encountered situations where, for the sake of design documentation, multiple sheets are the difference between a schematic you can send in PDF and expect a reviewer to understand, vs a design that is functionally impossible to read. The best you could hope for is to split your schematic up on the one sheet such that it prints out just right spread across multiple pages (of paper or of a PDF), and that's near impossible to get good results from.

I know it's not very typical for hobbyists, but among engineering student groups where I send most of my time, we always try to get peers and professors to review designs both as a best practice to carry over into our later careers and as learning opportunities.
13
Client software / Re: Android client
My point isn't to say that a standalone logic analyzer (or MSO like we're talking about), and especially a pocket-sized portable one, is useless. My point is just that the goals of a LA are much more in line with a pc-teathered unit, so for the ease of design it affords, the USB-based LA is probably the best compromise.
14
General discussion / Re: QR in eagle
Not sure what the deal is, but I'm trying to use honken's newest release and I'm not getting anything at all! I go through the dialog, select top/bottom silk, and hit generate, a progress bar runs up, then... nothing. No new objects, no visible anything, not sure what the deal is.

Also, it's unclear to me: What does 'current layer' mean? In order for there to be a 'current layer', I have to be in some tool, but the ULP doesn't run in the context of a tool.

EDIT: Hmmmm, it dumps a .scr into my project directory that makes the code. Makes more sense now, but still unintuitive.

EDIT 2: Here's a much bigger problem: Looks like characters don't get escaped correctly - my end URL reads as http%3A%2F%2F......

EDIT 3: Got a chance to look at the code, it turns out that the urlencode() is an unnecessary step. Not sure where it comes into play in the api calls, but I just made the change in the first line of the main make_gr_scr function:
Code: [Select]
  //string url_enc = urlencode( url );
  string url_enc = url;

tl;dr: made a quick modification, version attached below works for me with URLs.
15
Open Bench Logic Sniffer / Re: FIFO wing to increase sample depth?
That's a very valid point, even if I only had a single byte, that's more than enough for lots of long-running serial analysis, for example 4 uart channels, two spi channels, so on. And the point here is that, where now I can have 4x the sample depth if I choose 1/4 the total 32 bits, using a wing I could have much much greater depth if 8 channels is enough.

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