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Bus Blaster JTAG debugger / Re: FTjrev
There is now an improved version of ftjrev.
Wil
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Messages - Wil
There is now an improved version of ftjrev.
Wil
2
Bus Blaster JTAG debugger / Re: Bus Blaster V3 TDO stuck at 1
Wil
3
Bus Blaster JTAG debugger / Re: Bus Blaster V3 TDO stuck at 1
I just received two Bus Blaster v3c from Seeedstudio and I face the same problems (TDO stuck at 1 ...).
With the original firmware I couldn't get any result with UrJTAG (from SVN) or any other tool.
So I built a programming file (.svf) using the constraints file from JTAGkey_test directory on the SVN [0] (with some lines commented out) and the Verilog source file used for BusBlaster v2 [1].
The resulting .svf file and the modified constraints file should be attached to this post (but I can't see them in preview mode).
Now I can get some results, but it's not reliable. It works once every ten tries.
I tried lowering the frequency, but with no significant result. Most of time I still get the "TDO stuck" error.
Sometimes it just simply works, and I can access the 5 chips of my test board. Then with no apparent reason it just stops working ...
Access to the onboard CPLD using the second channel is working flawlessly.
Next I will try to bypass the CPLD and I will try to solder the probe wires on both sides instead of using jumper wires.
Chip soldering looks correct compared to my old BBv2.
Ideas are welcome ...
Wil
[0] trunk/Bus_Blaster/buffer_logic/JTAGkey_test/BBv3JTAGKEY.ucf
[1] trunk/Bus_Blaster/buffer_logic/JTAGkey-Verilog/jtagkey.v
4
Bus Blaster JTAG debugger / Re: [SOLVED] TDO stuck
One more info, I never had any problem accessing the onboard Coolrunner (xc2c32a-vq44).
This is probably a side effect of the "one axis" misalignment.
Wil
5
Bus Blaster JTAG debugger / [SOLVED] TDO stuck
I ordered my BusBlaster v2 almost a year ago from Seeed Studio.
From the beginning I had to struggle with the following messages with UrJTAG:
Code: [Select]
warning: TDO seems to be stuck at 0or
Code: [Select]
warning: TDO seems to be stuck at 1
And sometimes, for no reason, and without changing anything to the wiring, it simply worked.
Then I found why...
Here are some self-explanatory close-up shots of my BusBlaster, before I fixed it.
Pins at the top of the FT2232HL chip with almost no solder on them.
[attachment=2]
Pins at the bottom of the FT2232HL chip, misaligned but soldered.
[attachment=1]
Top view, misaligned chip on one axis.
[attachment=0]
I reflowed the FT2232HL with a hot-air rework station. Since then, my BusBlaster works flawlessly.
I thought i was worth sharing.
Cheers,
Wil
6
Bus Blaster JTAG debugger / Re: FTjrev
I forgot to mention that you need to modify the USB VendorID and ProductID
for FTjrev to work with the BusBlaster (with PicoTAP buffer logic).
Here is a patch:
Code: [Select]
--- ftjrev.c_orig 2012-04-26 22:27:05.000000000 +0200
+++ ftjrev.c 2012-04-27 09:43:18.000000000 +0200
@@ -80,7 +80,7 @@
uint8_t latency;
ftdi_init(&ctx);
ftdi_set_interface(&ctx, INTERFACE_A);
- if(ftdi_usb_open(&ctx, 0x8482, 0x1002))
+ if(ftdi_usb_open(&ctx, 0x0403, 0x6010))
return 1;
ftdi_usb_reset(&ctx);
ftdi_set_latency_timer(&ctx, 1);
I also managed to make it work with the JTAGKey buffer logic.
For this, you will need this patch (along with the previous one):
Code: [Select]
--- ftjrev.c_orig 2012-04-26 22:27:05.000000000 +0200
+++ ftjrev.c 2012-04-27 09:44:13.000000000 +0200
@@ -90,7 +90,7 @@
if(ftdi_set_bitmode(&ctx, 0x0B, BITMODE_MPSSE))
return 1;
setspeed(1);
- setgpio(9);
+ setgpio(8);
ftdi_usb_purge_buffers(&ctx);
return 0;
}
Modified source code can be downloaded here
(original code is licensed under the terms of GPLv2 or later).
William
7
Bus Blaster JTAG debugger / Re: FTjrev
Thanks for the information. You are right, it works with the PicoTAP
buffer (the reset pin is not used).
My previous tests where performed with the JTAGKey buffer, but it
seems that FTjrev doesn't know about the buffer enable pin.
Thanks again for your help !
Wil
8
Bus Blaster JTAG debugger / FTjrev
I'm trying to use my BusBlaster with FTjrev (nsa unaligned org/jrev.php) to reverse-engineer connectivity between chips on a board.
I can list the devices chain on the board using UrJTAG, but so far I can't get anything out of FTjrev.
Did anyone of you already tested this tool ? Is there another opensource alternative ?
Thanks,
Wil
PS: Sorry for the malformed URL, I had to find a way to bypass the 'first post spam filter' :).