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Messages - flubberlab

4
Open Bench Logic Sniffer / Re: sampling "end"
How about using TRGO for indicating both Trigger Detected and End of Capture conditions; rising edge for Trigger Detected, falling edge for End of Capture.
5
Project development, ideas, and suggestions / Re: DIY ultrasonic range finder
Looks interesting to do it all from scratch. Here is an alternative if you want some really low-cost pre-built stuff.

Some of the older Polaroid cameras used real ultrasonic range detection--up to 30 feet, I think. Just tear out the appropriate parts and add your controller chip.

I have been finding the cameras--especially the Spectra model--occasionally at local thrift stores (e.g. Goodwill) for less than $5. The big round ultrasonic transducer is visible and easily identifiable.

Other consumer products that use ultrasonic detection are home intrusion alarms and garage car parking systems. I have found both in thrift stores for cheap as well.
6
General discussion / Re: DIY soldering paste stencils (SUCCESS!!!!!)
@erdabyz,
In case you're looking for alternatives to applying the pattern, perhaps you could run your foil directly through a laser printer.

Interested in whether or not the toner would be applied correctly directly to metal, I once ran a piece of normal thin aluminum foil--taped to a piece of paper--through a laser printer. It worked great. I forgot whether or not I had removed the fuser first, but I'm pretty sure it was in.

So, theoretically, one could print a PCB or stencil directly with a laser printer.

Of course, the issue is whether or not the material can negotiate the feed mechanism. I figure that the most important step is to get the pattern on the metal. I can always fuse it myself--I think. Just need to avoid sneezing...
7
Client software / Re: Jawi's Logic Sniffer client software - releases
@jawi: I'm really excited to see the switch to a different communications library. I ran some quick tests with OBLS, ols-0.9.5-b1, and WinXP Pro 32-bit SP3 to see how the communications went:

Sample Clock = Internal @ 20 MHz
Recording Size = 6k (manual)
Test mode = off
Noise Filter = off
RLE = off

Channel Groups  Capture OK?
--------------        -----------
0              yes   
1              yes
2              yes
3              yes
0, 1            no, upload hangs (progress bar goes just barely to the end, then stops), see log below
0, 1, 2        no, upload hangs(progress bar goes just barely to the end, then stops), see log below
0, 1, 2, 3      yes


Log for cancelled hung captures:

[11/23/11 3:34:28 AM - INFO  - logicsniffer.LogicSnifferDevice]: Attaching to COM17 @ 115,200bps (DTR = low) ...
[11/23/11 3:34:28 AM - INFO  -    LogicSnifferAcquisitionTask]: Starting capture ...
[11/23/11 3:34:28 AM - INFO  -    LogicSnifferAcquisitionTask]: Found Sump Logic Analyzer/LogicSniffer compatible device ...
[11/23/11 3:34:28 AM - DEBUG - rSessionManager$WindowStateListener]: Writing dialog-specific properties for org.sump.device.logicsni
ffer.LogicSnifferConfigDialog ...
[11/23/11 3:34:28 AM - INFO  -    LogicSnifferAcquisitionTask]: Detected device type: Open Logic Sniffer v1.01
[11/23/11 3:34:28 AM - DEBUG - rSessionManager$WindowStateListener]: Writing window-properties for org.sump.device.logicsniffer.Logi
cSnifferConfigDialog ...
[11/23/11 3:34:28 AM - INFO  -    LogicSnifferAcquisitionTask]: Using device profile: Open Bench Logic Sniffer

upload hangs here, so I click the "Cancel the current capture" button

[11/23/11 3:34:36 AM - WARN  -    LogicSnifferAcquisitionTask]: Capture interrupted! Only 6,144 samples read ...
[11/23/11 3:34:36 AM - INFO  -    LogicSnifferAcquisitionTask]: Decoding unencoded data, sample count: 6,144
[11/23/11 3:34:36 AM - INFO  - BackgroundDataAcquisitionService]: Acquisition successful!
8
Client software / Windows-based Client (VC++, MFC)
After repeated serial communication hangups with the Java-client (it could be just me), and to satisfy my urge to reinvent the wheel, I wrote the beginnings of a SUMP client. Since my experience is mostly with Windows and C, I used Visual C++ 2005 and MFC.

The client is pretty well tested (on WinXP Pro), but only offers a configuration and capture front end. Advanced triggers are not supported, RLE is unimplemented, and there is no waveform viewer. The captured data is exported to a VCD file for external viewing (I use GTKWave).

When/if I get around to it, the next step would be Advanced trigger support. It would be easy to add continuous (automatically repeated) acquisition and waveform display persistence (OR in the new data with the old).

Note: The Test Loop repeats so fast because it expects an immediate trigger condition and fast sample rate.
10
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
@dogsbody,

Thanks for your description; it really corrects my false assumptions about how the trigger works (and gives me the luxury of slacking on learning Verilog or VHDL!).  I can see why masking off bits is exactly opposite the "right" approach to disable a stage.

Here is what I have learned:
--- The mask and value combine to form the classic (on the analyzers I have used) "0, 1, don't care (X)" pattern choices (pattern 0/1/X = mask:value 1:0/1:1/0:?).
--- All stages are permanently active. Each stage either initiates a capture (if configured to do so) or increments the trigger level regardless of its mask.
--- If multiple stages have duplicate masks/values, the group acts together as if it were a single stage, and increments the trigger level only once. If any stage in a group of duplicate stages is configured to initiate a capture, then a capture will be initiated exactly once.

I think your idea of duplicating stages is clearly sound, whereas my idea of relying on setting the arm levels "out of range", is not (to me) obviously--without further analysis--effective for all possible cases.

Duplicating the triggers as you describe works in this simple application I tried. Here are some examples (capture on low to high edge) that illustrate what works and does not:

Stage Level Pattern Capture?
  1    0      0      No   
  2    1      1      Yes   
  3    3      X      No   
  4    3      X      No   
Does work, since desired trigger occurs before "unused" stages 2 and 3 are armed.

Stage Level Pattern Capture?
  1    0      0      No   
  2    1      1      Yes   
  3    0      0      No   
  4    0      0      No   
Does work, since duplicate stages 1, 3, and 4 act together as a single stage.

Stage Level Pattern Capture?
  1    0      0      No   
  2    1      1      Yes   
  3    1      1      No   
  4    0      0      No
Does work, since duplicate stages 1 and 4 act together as a single stage, and stages 2 and 3 act together with stage 2's "yes"-capture overriding stage 3's "no"-capture.

Stage Level Pattern Capture?
  1    0      0      No   
  2    1      1      Yes   
  3    0      X      No   
  4    0      X      No   
Does not work, since "unused" stages 2 and 3 bump level too soon, overriding stage 1. The trigger is effectively "match level 1".

Stage Level Pattern Capture?
  1    0      0      No   
  2    1      0      No   
  3    2      1      Yes   
  4    2      X      No   
Does work.

After some reflection, I guess I blindly jumped into this topic in which to post these functional details because your spec has me thinking what a great single-point source it is to put it all. Maybe the Wiki where ian duplicated your spec is more appropriate, and maybe I could contribute there instead of dropping little crumbs here...  Thanks for having taking on here the deails that are SUMP-common, especially since I understand that your main goal was to do the HP16550.
Walt.
11
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
I noticed something unexpected with the 3.07 Basic/Legacy trigger operation that I think is a good candidate to be described in the spec/guide.

I observed that a trigger stage increments the trigger level even though all of its inputs are masked off. Is this the intended behavior? I expected that the level would not be bumped by the stage configured as such.

This lead me to the question "How do you disable one or more stages?" A workaround I used was to arm the unused stages at a level greater than or equal to the arm level of the capture stage/s with the highest arm level.
12
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
I know what you mean.

I guess the desired content depends on who the spec is written for. I have considered it first and foremost as an interface spec that targets software developers that need to know precisely what the OLS can do and how to make it do it. Perhaps a useful thought is something like this: if it has a command description that includes the numeric opcode and parameter bitmap, then why not go ahead and describe as precisely and completely as possible what the effect of the command is?

I think the fact that it is such a sweet document tempts one to use it as a user guide as well. In an ideal world, I think there would exist both a programmer's guide (your spec) and a user guide.

The way I look at it is I can probably figure out how to use something with only a programmer's guide, but I can't write software to run it with only a user guide. I'd have to reverse-engineer the thing to do that (i.e. create my own programmer's guide).

Thanks for listening.
13
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
Beautiful. Thanks.

How about another little interface revision: The device returns (readCount + 1) * 4 bytes, so perhaps
"The read-count specifies the number of samples (read_count = (num_samples/4) - 1) to be returned to the client on your PC (one byte per each enabled input channel group). The delay-count specifies the number of samples (delay_count = (num_samples/4) - 1) to capture -after- the basic or advanced trigger fires."
15
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
The Demon Core spec is so nice that I thought it deserved some interface details that I think would be especially useful to client developers.  I have attached a revised spec (Track Changes is on). Two operational details that I ran across but have not verified in other docs are
1. Need Reset after capture to make sure next trigger works correctly, and
2. Need basic trigger mask and values copied to upper groups for Demux mode

I found that if I did not reissue a Reset command after a capture, then sometimes the OLS would hang in an armed state on the next capture.

Can someone verify whether or not my revisions to the spec are valid?

One question: Is RLE compatible with Demux mode?

Thanks.


EDIT: Well, it looks like the file is too big to upload. If there is interest in the Word doc, where mayI put it?

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