A HID based search for the OLS in the USB database is exactly what I do now. It works fine, but takes a lot of setup for the API call's, and is noticeably slower.
I could have cheated & hardcoded the strings, but I was feeling extremely annoyed with Microsoft, and d*mn determined to find a way to get that description. :-) -- IED
Yes, enable/disable on terms is simply for ease of use.
The op blocks connectivity is not infinitely flexible. The drawing accurate shows the connections -- which mirrors the 16550 pretty closely. However, by using "a-only" or "b-only" op-blocks (ie: disabling unused inputs), you can combine any term with another to some degree.
If the user needs a really complex function, then they must assign terms to permit it. -- IED
1/2) Parameters look good. Might want to add an enable/disable flag to the term inputs though. See below.
3) Yes, the "op1/op2/op3" operators allow a single input. They are LUT tables themselves & can be configured to implement -any- function. Figure 23 in the spec contains the example "A" & "B" columns accordingly. In the HP16550, the various inputs (ie: a/b/c/range1/d/edge1/etc...) had an Enable/Disable control. The op stages only offered "and/or/xor/nand/nor/nxor". In the case of the OLS, the client needs to configure the op1/op2/op3 stages to match the input enable/disable state.
4) Currently, the hit-term counter tracks total hits. To handle contiguous hits, you'd need to use the "else" state. So if you miss on the hit-state, configure an else-term to jump to another state -- or even just back to the same state. Taking the else-path zeros the hit-count.
Altera & Xilinx have command line versions of their tools (ie: ngcbuild,map,par,etc...) Other tools are Cadence NC-Verilog/Simvision for design simulation & waveform viewing. Also use Synopsys VCS there. Gotta have both, otherwise Cadence & Synopsys sales people do unnatural acts with pricing.
For fpga synthesis, I prefer Synplify-Pro. Xilinx synthesis is buggy (never ever use the verilog "generate" with XST). Altera is not so bad. The Synplify retiming engine in particular is much much better than anything Xilinx or Altera offer.
For fpga work that's pretty much it, excluding the umpteen scripts for automating stuff. -- IED
Xilinx (& Altera for that matter) develop their GUI apps for Windows & port to Linux as an afterthought. If it works, wonderful. However, the Linux versions simply don't get the same level of Q&A testing. There are various instabilities under Linux flavors I'm aware of that aren't present on Windows.
I use Linux at work (specifically RHEL) for fpga development, however I stick to command line tools for builds. The GUI IDE stuff is just too flaky. -- IED
Interesting. Definitely a departure from the legacy 2.12 RLE mode. A client supporting this would not be compatible with 2.12 any longer, or would have to have specific support for both 2.12 & the newer cores.
I'm not opposed -- obviously I have no problem changing things. :-)
My only concern is logic size increases. The 16550 trigger stuff kinda fills things up in the demon-core.
Jawi & crowd really need to weigh in on this one... -- IED
The problem David just fixed refers to how demux mode packs two samples per capture word.
With the legacy 16-bit ddr samples, two samples are present in each 32-bit capture. The rle-encoder sees a 32-bit word & compresses accordingly. Obviously the client needs to be aware of that when decoding. This is how the 2.12 fpga worked.
The newer fpga's support 8-bit ddr samples with rle encoding & that adds a new twist. The fpga handles those as 16-bit captures, with 16-bit rle counts. Again something the client needs to be aware of when decoding. -- IED
Here is a version that properly detects/describes the Logic Sniffer on Windows XP, Vista & Win7. Turned out to be really quite annoying to fix.
The registry entry for the Logic Sniffer had a description line stating "Logic Sniffer". However, none of the setupapi functions would return that. Only "Communications Port" or the location info. XP was fine. Not Vista or Win7. Nice improvement there Microsoft. Ug.
So now ols_winloader plies the depths of the USB database, and grabs the product description direct.
The basic trigger should have no impact on the rle encoder.
The v7 fpga stores normal data until armed, then enables rle recording. It does create a potential hazard, since if input data is changing on the rle-flag bit it could spoof bogus rle-values. I've made a tweak to fix that for my next release.
For 8-bit samples, if you ground bit7 does the problem still occur? -- IED
[quote author="miro"]it would be great to have _ANY_sampling_rates_ option[/quote] Any sampling rate supported by the fpga divisor at least... Still going to be (100Mhz / divisor-count). :-) -- IED
I'm not seeing anything wrong with the fpga in handling of 24-bit captures, in normal or rle-mode.
Jawi's client 0.9.3.1 seems to work fine also. I'm sampling a 1Khz signal on pin15, and all is well with group 0, 2, or 3 disabled. Haven't tried the git image though.
Can you try 0.9.3.1 & see if your problem goes away? 0.9.3.1 has an annoying problem with not retaining settings, but rle captures work fine. -- IED
The rle-counters are the same size as the samples. Thus in 8-bit or 16-bit mode the counters are smaller. In 8-bit mode, you only get 7-bit RLE counters. In 16-bit mode, you get 15-bit counters. The MSB is reserved for the rle-flag.
In 8-bit mode the maximum number of samples (even with non-changing data) is (24k/2) * 128 = 1.5M samples. At 100Mhz that fills very quickly (~15msecs).
In 16-bit mode the max is (12k/2) * 32768 = 192Msamples. So about 2 seconds at 100Mhz.
The missing events in group1 are a little puzzling though. I'll double check things when i get home. -- IED
The attached ZIP contains the Inkscape SVG file I used with the Ponoko laser cutting service. It's derived from J.J. Shortcut's design. I used 3mm thick clear acrylic plastic.
For a tight fit, you should install headers in the UART, ICGP, & ROM-ISP locations. For the buttons, a dab of glue stick holds the square plastic cutouts in place.
Install Inkscape & you can customize it if you like.
When in the bizarro state, does hitting the RESET button on the OLS do anything? Do you hear the Windows USB unmount/mount tones? Should be equivalent to plugging/unplugging the device.
Next, what happens if you try a different USB port? Windows will probably assign it a different COM port number, which should unglue whatever got fouled up.
