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Messages - dogsbody

4
Open Bench Logic Sniffer / Re: Ground for External Clock
[quote author="dogsbody"]Strikes me that when the board is revved it would be sensible to add two ground pins to the connector, one for the clock and one for the trigger.[/quote]
Yet another thing on the wish list. 

I'd also like to see a dedicated row of grounds next to the input header pins.  Would allow using shielded probe wires (like on the HP16550), and/or grounding off unused ports easily.    High impedance pulldowns on the headers would be nice (100K SIP's).  A DAC for programmable threshold voltages.  A larger fpga with external SDRAM, etc....  :-)

Alas, all unlikely...
-- IED
5
Open Bench Logic Sniffer / Re: Ground for External Clock
The clock cannot be more than 100Mhz.  The fpga can DDR sample off that to achieve 200Msamples/sec, but the core logic is limited to 100Mhz.

The lack of a ground header near CKI is a problem.  There are two capacitors off to the right though (C11 & C12).  You could solder a header pin there.  Not a perfect solution I know.

The fpga clock input needs to be clean, so you'll also likely need some type of termination.   
-- IED
6
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
Trigger Sources:  There are two range detectors, two timers, two edge detectors, 10 pattern matchers.

Trigger Sums:  The above trigger sources are combined using trigger sum's.    What I call a complex trigger is anything that combines two or more trigger sources into a single sum.  A simple trigger would be a single trigger source only.

Trigger States:  Each trigger sequence state (trigger state machine) can use different trigger sum's for storing, matching, or else conditions.  Each trigger sequence state can also have a totally different set of trigger sum's from any other state. 

In other words, any state, can use any trigger source, in any supported combination, in any order.  Trigger sources can also be reused in any/all trigger-sums in any/all trigger-states. 

So yes, your example in #4 is totally doable.  ie:

State0 :  Set match-sum = (trigger1 AND trigger2) OR trigger3.  If hit, advance to next state.
State1 :  Set match-sum = (trigger4).  If hit, start timer1 & advance to next state.
State2 :  Set match-sum = (timer1-trigger AND trigger5).  If hit, advance to next state.

The trigger could be more complex.  You can also use trigger sum's to control what gets sampled, or use the "else" state to jump backwards.

For example, a decoder looking for a specific value on a serial line:

Configure Edge1 to trigger on rising or falling edge of clock input.
Configure Trigger1 to match 0 on data input.
Configure Trigger2 to match 1 on data input.

State0 : 
  Set capture-sum = Edge1.  If capture-hit, store inputs.
  Set match-sum = (Edge1 AND Trigger1).  If match-hit, advance to next state.
State1: 
  Set capture-sum = Edge1.  If capture-hit, store inputs.
  Set match-sum = (Edge1 AND Trigger2).  If match-hit, advance to next state.
  Set else-sum = (Edge1 AND Trigger1).  If else-hit, goto state 0.
State2 : 
  Set capture-sum = Edge1.  If capture-hit, store inputs.
  Set match-sum = (Edge1 AND Trigger1).  If match-hit, advance to next state.
  Set else-sum = (Edge1 AND Trigger2).  If else-hit, goto state 0.
State3: 
  Set capture-sum = Edge1.  If capture-hit, store inputs.
  Set match-sum = (Edge1 AND Trigger2).  If match-hit, start timer1, advance to next state.
  Set else-sum = (Edge1 AND Trigger1).  If else-hit, goto state 0.
State4:
  Set capture-sum = Edge1.  If capture-hit, store inputs.
  Set match-sum = none.
  Set else-sum = Timer1.  If else-hit, goto state0.

The above trigger looks for a "0101" pattern on the data input, and only evaluates the data on a clock rise/fall.  It also only captures data on the clock edge.  After finding the pattern, it continues capturing on clock edges until the timer elapses.

Hope this helps.
-- IED
7
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
Dimitar, yes, your example could be handled.  Each of the sum_capture / sum_hit / sum_else could be different though (a/b/c/d/e/f/range/edge/timer/etc...), combined logically however you like.

Only those states, the corresponding capture/hit/else sums, and any trigger terms enabled by said trigger sums need be programmed.
-- IED
8
Open Bench Logic Sniffer / Re: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Ti
The advanced triggers are fully implemented.  No additional LUT's / design changes are required.  Example C code for programming them is even provided in the spec.  Trigger configuration is handled entirely through the standard SUMP interface.

It's definitely non trivial to configure though.  I pushed all complexity (of configuration) onto the client, since it simply wouldn't fit in the fpga.

The original simple trigger terms are bound to a given state, and the state can only increment upwards.

The advanced trigger terms are decoupled from states,  so they can be reused.  There is a new layer for combining multiple trigger terms algorithmically (and/or/xor/etc) which can differ by state.  Finally there is the expanded state machine which supports sixteen states each supporting if-then-else clauses with arbitrary jumping (on the else case).

Best approach to implementing something is probably small incremental adds.    ie:  Start by implementing the current simple GUI using the complex trigger.  Next, expand it to 10 states since there are ten normal trigger terms.  Then add support for converting states to be range or edge checks.  The if-then-else states, with trigger sums, etc... can wait for later.

Jawi claims to be working on it, but I suspect his time is limited these days.

-- IED
9
Open Bench Logic Sniffer / Re: Not capturing anything
Yes, it's pretty common.  The buffer inputs are floating.  They need grounding or pulldowns to quiet things.  For example, attaching 100K SIP resistor networks to the input header can help.  Have fun!
-- IED
10
Open Bench Logic Sniffer / Re: Not capturing anything
The OLS is capturing at 200Mhz, which is 5ns resolution.  The sample buffer can only hold 120us (0.12ms) of captures total at that rate.    At a 50ms SPI signal toggle rate, you won't see anything. 

Try a -much- slower sample rate.  32Khz would yield 750msecs of captures.

The trigger causes it to start capturing the instant channel 0 is high.  Perhaps try a trigger that looks for a transition instead (ie 0 ->1) would help? 

ie:  Set stage 1 to detect 0 on ch0, then stage 2 to detect 1 on ch0.  Only check the "Action" flag on stage 2 to start captures.

Cheers!
-- IED
12
Open Bench Logic Sniffer / Re: DAC capture in Synchronous Mode
You want to use CKI (external clock input).  It's not buffered, so add a voltage divider to knock the 5V down to 3.3v. 

The TRGI is the external trigger input to the logic analyzer.  ie: what tells it to start capturing data.
-- IED
13
Open Bench Logic Sniffer / Re: Failed update
Just so I'm clear... 

Did you download everything -fresh- from the links I provided?

When updating the fpga-bitfile with olswinloader, did you clearly select the COM port your OLS was connected to? 

olswinloader should highlight the COM port it thinks an OLS is attached to in bold font.  Do you see that?

Was anything -else- shown in the olswinloader COM port list?

Was anything else running on your PC attempting to access the COM ports?  Only one app can access a COM port at a time.  If you had Jawi's client running (for example), that might interfere with the update.  Perhaps try the update after rebooting.

Did you try plugging the ols into a different USB port on your PC?

One additional thing to try is manually entering bootloader mode to download the FPGA bitfile.  Use the PGC/PGD short trick (as mentioned before), and select "OLS-HID" within olswinloader.  This method bypasses the COM port layer.  Can you download the fpga bitfile then?
-- IED
14
Open Bench Logic Sniffer / Re: Failed update
Sounds like you need to update the PIC firmware, or it didn't take.  Seems to happens occasionally.    I've copied the following from another post of mine:

-------------------------------------

Plug the OLS into your computer. 

Short the PGC & PGD pins using a screwdriver/jumper while pressing & releasing the OLS reset button.  The OLS should connect as a HID device. 

Start ols_winloader (make sure you're using latest version) & it should appear in the list as "OLS-HID".  Select the v3.0 PIC firmware hex file & download.    You must use PIC v3.0 firmware if you want to use the Demon core fpga (3.07).  Once complete, the OLS should reset & connect as a COM port again.   

Now update the fpga bitfile to the Demon core v3.07.  Start ols_winloader again.  Select the OLS COM port.  Select the bitfile & download.

Grab images from:
olswinloader: viewtopic.php?f=23&t=1636
pic: viewtopic.php?f=23&t=1915
fpga: viewtopic.php?f=23&t=1711

Good luck!
-- IED
15
Open Bench Logic Sniffer / Re: Bricked OLS?
Sounds like the PIC firmware didn't take.  You need to fix that first.    Plug the OLS into your computer. 

Short the PGC & PGD pins using a screwdriver/jumper while pressing & releasing the OLS reset button.  The OLS should connect as a HID device. 

Start ols_winloader (make sure you're using latest version) & it should appear in the list as "OLS-HID".  Select the v3.0 PIC firmware hex file & download.    You must use PIC v3.0 firmware if you want to use the Demon core fpga (3.07).  Once complete, the OLS should reset & connect as a COM port again.   

Now update the fpga bitfile to the Demon core v3.07.  Start ols_winloader again.  Select the OLS COM port.  Select the bitfile & download.

Grab images from:
olswinloader: viewtopic.php?f=23&t=1636
pic: viewtopic.php?f=23&t=1915
fpga: viewtopic.php?f=23&t=1711

Good luck!
-- IED

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