This is my project for 74xx competition. I built a PLL synthesizer for use in the radio tube-style. The project consists of 21 logic chips. Pulses from the pulser counts up and down. The frequency is displayed on the nixie tubes. The system automatically stops at 88.0MHz and 108.0 MHz. To main freqency added is 10.7 MHz (f VCO= f set + 10.7). CD4059 works as a programmable BCD divider. I plans to build a radio tube with synthesis but do not have enough time.
sorry for english but I google translated from the Polish
