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Messages - Bustar
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General discussion / Re: Missing DSP, Audio, Analog.
Thanks for your comments. Appreciating your assistance. Hoping that you had a good weekend.
[quote author="Bustar"]
I have worked toward selecting an alternate pair of chip sets. At the moment, the TI set is led by the TMS320C6712D MSP and the Analog set by ADSP-21261 or 21262. All are floating point, and as usually seems the case, each also has fixed point. Each also provides an entry point that could be migrated upward in processing speed if needed to adjust to later findings.
[/quote]
Typical of the cited TI, Analog, DSP or Cortex M4 offerings, these include moderately deep INTERRUPT and DMA structures. The use of these with suitable time base controls, become vital to managing the iterleaving of multiple processes. This seems to have much more potential for my multi-stream instrumentation work than to most audio applications. And this is consistent with my previous observation that - -
'....the sampling is not 'real time', but has gaps sufficient to support other ongoing processes, including dual sampling rates.'
So by dual rates, I had in mind an upper rate of about 42 khz to cover the higher end section of the analog bandwidth in the region of 12 khz to 15 khz, with the lower boundry of that section being around 300 hz due to filtering to reject the emissions of the 60 cycle power lines and some of its low harmonics.
The second portion of the dual sampling rate would be around the 100 hz rate that I cited to cover the analog range of 0.5 hz to 50 hz. This portion would have separate signal conditioning treatment by using a low-pass filter with a 50 cycle cutoff prior to digitizing, with this having the purpose of preventing ailiasing due to Nyquist violations. It may also modestly reduce the noise that can result from the presence of unneeded bandwidth.
If this dual sampling rate concept were not deployed, application of the 42 khz sampling rate to the lower bandwidth signal range would result in an over-sampling rate ot about 400 to 1, which would unnecessarily increase the data input by this amount for this lower portion of the observed spectrum. And it would increase the amount of wasted processing by some exponent of 400 times for this portion of the bandwidth.
The keen advantage of making such provisions within the signal conditioning section, permits the standardized programable sections of the high density digital processing to be adapted to a great range of potential 'open sytems' analog applications, with my immediate case just being one of those types. This is an approach that permits the range of those applications to be explored, while serving more immediate goals. It also has the intention of seeking to keep most of the dense chips with very high pad counts within the standardized digital section where the complex multi-layered type boards are deployed, while trying to minimize the board tech needed within the signal conditioning adapters where changes are more often needed to meet differing applicaiton requirements.
Programmable gain instrumentation amplifiers are becoming more available. A couple of the typical types are the PGA280 from TI and the AD8231 from Analog Devices. When a handful are deployed at prices of around $3, it is possible that costs could be a limiting factor in some cases. I don't consider them an 'elaborate addition'.
Noise level considerations are usually considered more critical in the up-front stages of most processing streams. That view may be carried over from communication radio receiver practices. Neither does that view usually prevent the careful deployment of needed gain. As part of signal compatability reviews, all noise sources need consideration. By deploying scaled gain up-front, the level of desired signals can be elevated to a higher portion of the dynamic range, which can reduce their noise susceptability in later processing stages. It is a subject for analog signals that needs continuing attention.
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General discussion / Re: Missing DSP, Audio, Analog.
Your point about the noise hazard within the mixed tech chips is well taken. There are some early versions of the Cortex-M4 MCU plans that included the gain controlled pre-amps on the same chip. This concerned me, and those seemed to have been dropped from later versions, most likely for the reasons that you cited. The hazard of having the ADC's in the mix on the processor chip is different but will bear watching. It is my reasoning the signal conditioning front-end will include scaling and filtering, and this is the area where the SNR noise floor should be established as needed to adjust and calibrate the performance of some sensors.
My view of the sampling time base has also been strongly altered. From the outset I had expected to suppress the widespread prescence of 60 cycle power line radiation and some of its harmonics, while retaining an upper frequency pass band of 10kc to 15kc. But it was observed the underlying process changes at a materially lower rate, thus my statement of needing 'real time' operation can be materially relaxed, although sampling does need to be synchronous, with finework. From a software viewpoint, this becomes a dividing point which splits this thread between audio and precision analog needs, where I consider audio to be more of a real time continuous process.
Added emphasis for the analog processing in the frequency band of 50 cps and lower has developed. Presently, it is thought this can be sampled at a materially lower rate, and this can run concurrently with the higher rate of sampling needed for the upper band range to 15kcps. This is considered feasible because the sampling is not 'real time', but has gaps sufficient to support other ongoing processes, including dual sampling rates.
In all cases the Nyquist sampling limit would be honored in conjunction with the related front end filtering. That always seems to be associated with the upper end of the bandwidth being processed. The factors affecting the lower frequency end of the ranges are not so often discussed, and are not so clear to me.
For instance, if a bandwidth up to 50 cycles were to be processed, the usual rule would indicate the minimum sampling rate would be 100 cps for that process. And if acquired data was being FFT processed into a spectrum line of 1024 points, I may assume a frequency range of 0.5 cps to 50 cps covering two octives, would leave 10 samples per cycle to cover each cycle within the lower end of the frequency range at 0.5 cps. This is not a sure thing because the factors establishing this low end of the range are not usually cited. Of course, this range is more typical of some geo-physical or medical applications, rather than audio.
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General discussion / Re: Missing DSP, Audio, Analog.
Given the widespread licensing and strong market penetration of the ARM sets, it seems likely there will be competitive influences to broadly produce such offerings from a variety of sources. Freescale has defined a chip set in a series of K10 to K70. The K20 and K60 are of particular interest because they include the 16 bit ADC and 32 bit DSP, as well as USB and deep DMA, with much else.
A link to such info is - -
Kinetis ARM Cortex-M4 Microcontrollers
Freescale's new mixed-signal MCU family based on the new ARM Cortex-M4 core. ... Kinetis K20 Low-Power MCU with USB On-The-Go; K30 Kinetis K30 Low-Power MCU with Segment LCD
http://www.freescale.com/webapp/sps/sit ... .jsp?cod...
Then selecting - -
K20: Kinetis K20 Low-Power MCU with USB On-The-Go
And finally selecting - -
Kinetis K20 Family Product Brief
- - leads to a handy 40 page summary briefing for the K20. There is a broad set of docs here that were mostly updated just within recent months, all of which cover the chip family more broadly.
The availability of such chips may enable a development concentration upon the signal conditioning to match the needs of the analog input sensors. It may also reduce and simplify much of the needed board circuity.
For those needing more than 100 or 150 Drystone MIPS, perhaps the briefing document for the K60 will be of some possible interest.
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General discussion / Re: Getting started in the ARM world
Thanks for the reading and for your contributions.
Needed to be alerted about I2C versus I2S.
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General discussion / Re: Getting started in the ARM world
This may be rather out of date, but in doing some STM32 scanning, was feeling interested and surprised by your findings per your statement that follows ---
Quote from: brian
I
I would be sure that the peripherals you want are there. I wanted USB host, external memory interface and I2S on a chip, STM32 doesn't have any such chips.
Have some feelings there may be some misunderstandings caused by the flyer descriptions.
The trailing notes were collected in bits and pieces.
a. Some times the circuit flyer refers to I2S as SM Bus/PM Bus.
b. Their DMA section references memory source and destination operations. And they also mention that 80 GP I/O's are assignable to the 18 pins used for external interrupts. That seems rather obsecure, as a possible external memory expansion.
c.They do feature the STM32 as a low pin count unit. So they may lack room for ext memory additions. Unless you have resolved the answer, maybe it is worth a call to follow their advice to call their local sales agent.
My flyer notes are as follows - - -
STM32F100x4 STM32F100x6
STM32F100x8 STM32F100xB
Low & medium-density value line, advanced ARM-based 32-bit MCU
with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces
â– Up to 8 communications interfaces
– Up to two I2C interfaces (SMBus/PMBus)
â– DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs, USARTs and DACs
2.17 I²C bus
The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.
It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.
2.14 DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, DAC, I2C, USART, all timers and
ADC.
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CPLD programmable logic / Re: cpld wish list :)
My first and only wish so far has been already granted. In accessing the XILINX software, they offered to send a DVD. So I filled the order form. The whole deal turned out to be free, as I had checked off the free shipping option (I did not try the others.). // The only kink was the form indicated they would not accept the use of my P.O.Box which is much more secure than my front porch in the city. Appears the size is at least 3 or 4 GB.
Had not upgraded my ISP connection due to many relocations in recent times for health care reasons. Not sure what I need, but it may be logical for me to move from dial-up to DSL, but I have no idea which one. // This CPLD sandbox does have my attention. Had designed a couple of minor state machines in early bipolar FPGA with fusible links. Aged stuff. Thanks for the handy start with CPLD.
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General discussion / Re: Missing DSP, Audio, Analog.
The concept of using the 10 or 12 bit converters often found on a controller board could be useful at much higher resolutions especially for prototype investigations. Either way, it was favorable that Analog Devices had issued the Circuits Note to validate the approach per this 1/19 citation as - -
"Just found an interesting Circuit Note from Analog Devices CN-0096 which provides a 4 page description supporting the use of adjustable gain amps to increase the resolution of A to D converters. Seems to support the descriptive paragraph that I included yesterday."
Spending time with family affairs for a few days, if the weather does not muck things up. Not going AWOL, just other fun. Just avoiding uncertainty or any concerns at DP.
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General discussion / Re: what architecture do you use?
Took a flyer because it was previously uncertain if you had any FFT applicaitons. DMA seems very useful for related I/O linkages, like A to D. But with your STM32 connection, wonder if you noticed the recent announcement by ST Micro. ARM had announced M4 core support with option of an embedded Floating Point Unit. More recently STM announced they would sample that chip this year. Given their previous involvements with open sys uses that caught my attention. Also along that line, have you noticed the Seeed offering of Maple?? All thought to relate to STM32 but maybe I am offbase, unintentionally.
Posted by: deyjavont
« on: January 19, 2011, 10:54:18 PM » Insert Quote
@ Buster
I wouldn't really know about FFT on the STM32. I haven't looked into it. I use the STM32 mainly for low power, and for full parallel DMA with the display
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General discussion / Re: Moving day
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General discussion / Re: Missing DSP, Audio, Analog.
This approach may permit a simple hardware setup to permit my user clients to do some investigation of actual acquistion and processing needs. This can limit the stakes that otherwise depends upon to many assumptions. It may permit the avoidance of a multi-layer processor board and permit the concentration on the mostly analog signal conditioning board, especially during prototyping.
Now thinking about working this processing problem backwards for openers. Considering the questions of - - What rate would result from making this a minimal dongle using USB or Eithernet interfaces with the processing and control done in a PC? Or processing done in a current microcontroller board with or without connected PC?
For prototyping purposes, the forgoing cases could consider supporting just one datastream rather than four. It could also support sensor validations, to help hedge the overall efforts. Prototyping with two channels rather than four may also be a useful option. Many choices open by employing 'burst mode'.
The recent demo's of audio spectrum dongles in DP and back-engineered software could also come into play as useful shortcuts. All quite unexpected.
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General discussion / Re: Missing DSP, Audio, Analog.
Think my use of 'roughly' led to part of fog. Also, slower sample speed may be allowable.
Many micro controllers include 10 bit A to D. Lets say that its gain scaled to be 0 to 1 volt max range, so LSB is a millivolt. If DAC is set to 3 volts, then the A to D can read 3 to 4 volts in 1 millivolt steps from the A to D. The value read by the A to D is then added to the DAC setting to get the true value being measured. All as coarse and rounded example, ignoring any sign bit. By rounding I mean the 10 bit A to D would have an actual range of 1024 millivolts rather than one volt.
If the rough tracking DAC was settable within a 0.1 volt range of the signal, then gain going into the A to D could be increased to expand the resolution to 100 microvolt steps.
Noise is not considered critical when working with larger signals that are higher in the range.
The DAC is bypassed when working down at the noise floor or below. In this case the SNR of the signal conditioning and gain setting amp are expected to dominate the overall noise limitations. Thought this could be a way to expand the usefulness of controllers having 10 bit A to D and 10 bit DAC by just adding external amp chip with gain that was under digital control. Perhaps an added differential amp is also needed. This is currently of uncertain use to my specific applicatiion or prototyping needs.
==========================================
Been finding possible ways to limit needed processing bandwidth which I need, due to- -
a. bandwidth due to Nyquist limits are one thing
b. bandwidths needed for very slowly changing geo-physical type measurements are quite another
This is the basis of the 'burst mode' that I have mentioned. Two spectrogram lines (2X1024 samples) could be converted and stored in local RAM at a rate to satisfy Nyquist limit. This is enough data to support one line of spectrum data when the windowing is applied in processing the two line input block.
Then a much longer period is allowed to unload the local RAM and to process the line of data before another acquistion cycle is needed.
Expanding the acq cycle block to 3X1024 samples would permit two spectrum lines to be derived with a coherency to permit immediate cross correlation to be computed between the line pair. (cont)
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General discussion / Re: Missing DSP, Audio, Analog.
Reconsidering possible alternatives to the 18 bit resolution of the A to D, with a possible move to 16 bits which has a lot more offerings. This seems possible without a loss in dynamic range by introducing gain switching into the signal conditioning within the front end section. (Some A to D's have such switching but I prefer not to depend upon that case.) Since the higher resolution was of interest when working near or below the noise floor, having gain under program control near the input stage from the sensors seems like a possible solution. This is also a means of scaling change, and its front-end placement should be superior from the standpoint of SNR. Such selectable pre-amps are available but the function could merge with bandpass filtering in the front-end, within the signal conditioning. This could be activated as an adaptive mode change, most likely at the spectrographic frame level or higher. Although working at audio frequencies or lower, the monitored parameters have an even slower rate-of-change, which permits such mode changing.to be considered feasible.
[/quote]
Just found an interesting Circuit Note from Analog Devices CN-0096 which provides a 4 page description supporting the use of adjustable gain amps to increase the resolution of A to D converters. Seems to support the descriptive paragraph that I included yesterday.
Happen to have their AD8231 amp flyer in hand ($2), G=1 to 128 in binary steps. I also think they have been promoting a recent version with better specs.
Have also wondered if it is feasible to run the output of a DAC into one leg of a differential input to an A to
D as a means of expanding the resolution in the upper portion of the input range, when the DAC is roughly tracking the input signal. Fussy stuff and not so vital as in the lower signal ranges. This assumes the DAC has higher resolution.
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General discussion / Re: Missing DSP, Audio, Analog.
Since there are four analog dataflow channels, they could be operating at differing gain settings. It seems of interest to adjust the digital data prior to FFT, as it can be combined with other calibration adjustments that would be useful to the monitoring and adjustment of the system performance. That would also facilitate cross-correlation processing between channels or the computations of other vector relationships.
Perhaps I should withdraw from using the term of 'real-time'. My cases have freedoms that I have mentioned as burst mode previously. This is quite a difference from other applications that process speech or music. I had mentioned using sliding windows in the FFT processing. This is often expected to use a window width of 128 samples/window within a 1024 sample line, which coincides with an 8 stream process (per channel). This is not a fixed case because the format values are settable, as is known to be useful to system optimisations. This being mentioned relative to your scaling observations.
I have worked toward selecting an alternate pair of chip sets. At the moment, the TI set is led by the TMS320C6712D MSP and the Analog set by ADSP-21261 or 21262. All are floating point, and as usually seems the case, each also has fixed point. Each also provides an entry point that could be migrated upward in processing speed if needed to adjust to later findings.
Exploitations of the cited Burst Mode could also possibly lower the demands for processing speed for some applications. As a minimum case for slower processors, after acquiring two lines of input data samples, the cited sliding window processing could be completed to produce one line of output consisting of1024 data points. A delay in the sampling sequence may be tolerated prior to acquiring the next two lines of data, although it is likely the process should proceed with a coherent overall pattern. The consequences of adopting this scheme are currently TBD.
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General discussion / Re: what architecture do you use?
Reminds me that I saw the SHARC support software on a limited time discount offer of only about $2K instead of normal case of around $7K, as I recall. Does not seem very inviting for the entry of minor players trying to get started, or is there an easier approach? Anyone have a reasonable offer approach that could not be refused?