[quote author="oliver"]I measured with my cat. and the 'fattest' headers I had where 0.66mm. The holes are 0.71 so that's 0.05 'bigger'[/quote]
Yes, but they are square pins. Most are 0.635mm square and that means you need holes >0.9mm to fit them. The datasheet will normally give you a recommended hole-diameter. Standard 2.54mm pitch headers normally use 1mm holes.
[quote author="oliver"]As for Via #41, the thing is, when set to 8 mil clearance, it doesn't come up in the DRC check. Unless that one is limited to 56 errors.[/quote]
I guess that too many DRC errors makes it hard to see what is failing what.
You'd want a transformer in there somewhere (as part of the switch PSU) to ensure isolation, but that is standard in most line-powered step-down PSUs. Then, 6A@18V is about 110W output. With 85% efficiency (and that is high for a 6.667:1 ratio), that means about 130W in. So, you need to dissipate 20W and that means a lot of heat.
So you want a lot of power minimal size; can be done, but that is not going to be cheap. Do you have to feed it from the AC line directly? What is the sizes you are talking about? Can you dissipate 20W?
If you want to design it yourself, then your biggest headache will be to create a proper switch-transformer and getting rid of the heat. All other stuff should be (relatively) easy.
You may want to design a solder-bridged in a way that the surface tension works in your advantage. F.ex. make them triangular (which is, unfortunately, very difficult to do in gEDA's PCB). Never mind, I'm wandering of on a cloud.
Via #41 is too close to the trace just above it (6.5 mil) on the bottom layer (netname CS103).
Changing the drill-size is often easier done in the source file (manually) if you need to do deviant things. At least, that is what I do as it is a lot faster. Anyway, in the preferences you have an option to change the increments.
The holes for the headers are 0.7mm. That is rather small. Normal 2.54mm pitch headers will not fit.
The real problems are the transitions of square wave in a logic signal. The harmonics can be used for analysis, but it is easier to look at the problem from a pulsed energy standpoint. The transition causes a pulse to propagate, which reflects if the line is not terminated. This happens regardless frequency of the logic signal.
For digital logic signals, it is easier to do the look at the problem using transient analysis and leave the harmonics on the side. Only when your digital square wave frequency gets somewhere at 1/10 of the cable wavelength (rule of thumb) it may pay itself to use harmonic analysis. Either way, you have to deal with the reflection, and that is always solved in exactly the same way: terminate your cable.
The use of a 100kHz square wave signal was meant to show that a relatively low frequency on a short (2.3m) cable can cause a lot of trouble (it rings a lot).
[quote author="oliver"]So the 'hole sizes' PCB puts in the gerbers, is something the board-fab will properly account for everything/anything? (itlead/seeed are my primary concerns at this moment). I'd expect they'd just take the drill bit that's in the gerber and drill :) Good service! too bad it's not listed on their fusion pcb service page :S Though having to widen a hole (even if it needs to be done 800 times, is easier than having to fix pcb traces I suppose :)[/quote]
Yes, the hole size in PCB is the finished hole size for Itead (and seeed is the same afaik). All modern manufacturers automatically adjust the CNC drill-file to match their production methods and standards.
The only factory I know of that still uses non-plated size is Olimex. Their drill-rack is also limited and have strict rules on how many holes you may have on a board.
For the (bad) old days you had the option to "Apply vendor drill map" (found in PCB under Connects menu). That was the way to make a generic design and then "fix" the holes to fit the vendor's default drill-rack. This sucked because you had to oversize the annular ring to fit multiple possibilities. So, small designs at the limit were a hell to design.
When I get boards made at a normal factory, then I can see that the holes are drilled with laser-drills (non-plated holes I can see this). No more problems that way.
BTW, I got pcbs from Itead with non-plated holes made. The trick was to decrease the annular ring to zero size and let the solder-mask cover the entire hole as if it was a via. DRC-check will complain, but this was a case of "I know what I'm doing". This way I get only one CNC-drill file and do not have to merge the plated/non-plated files manually (which is error-prone).
[quote author="oliver"]Actually, I want to use 8mil spacing, as the board-house has a 6 mil limit. 7mil is required (probably 0.2mm?) for U3 as that's simply the size it comes, and S1/S2, since I just picked the smallest resistor footprint. I'll increase the rings inner/outer as much as I can, while keeping the rest of the PCB intact assuming that they properly account for hole plating :)[/quote]
You either use metric mode (0.2mm) or imperial mode (8mil). Mixing the two is a bad idea and will make it a living hell when you have to fix small stuff. I normally design everything in 8mil or 10mil on a 5mil grid, which means that you get 8mil trace/12mil spacing or 10mil trace/10mil spacing. Only for very special cases I go down to a lower grid. Most SMD designs that involve 0.5mm pitched TQFP (or smaller) I exclusively use 8mil designs. I use all-metric designs only when I need to (still working on my library).
It should be noted that the power lines are normally a lot thicker and are mostly layed out before I put down the rest (including all the decoupling caps).
For solder-bridges, you may want to make your own design. A resistor may not work as they get small and the bridge may then be difficult to make.
Ah yes, reflectometer. Used one myself on coax-based Ethernet networks to find the gaps and see where folks had dropped the terminator. The modern version looks at fibers, which works very similar, just with light.
After seen and participating in the discussion about SPI problems viewtopic.php?f=2&t=3775 I decided that there was need for some hands-on explanation about digital signals and cables.
Cabling, and that means transmission lines, are not the easiest of topics and can make life hard for your electronic gadget. The main idea was to show what a cable does to your signal due to transmission line properties: http://www.vagrearg.org/?p=transline
[quote author="oliver"]As for the drill size, that's what's so annoying/confusing about half the PCB industry hanging to mil sizes, the other have to mm. (Read the blog! linked up!) In this case, I actually increased the inside of the DIP8 socket (to incidentally match the headers) as I was told they tend to get drilled small-ish and plating will make the hole even smaller. So I increased the inner diameter. I am afraid however increasing the outer diameter will make it that traces can't be routed in between anymore (in certain places) as it is already extremely crowded.[/quote]
The drill sizes you have in the PCB are interpreted by the manufacturer as "finished hole size", i.e. the size after plating. Only one factory I know of deviates from this practice nowadays.
The hard work is that you have to create your own library of components/footprints. I've gathered some from the gedasymbols.org site, but many needed tweaks to fit my needs and standards.
Another point is that I edit the pcb file manually to fix small stuff that is hard to do in the GUI, like bulk changes in drills and annular ring. I also have scripts that fix soldermask openings and clearance problems (mainly complex regex replace stuff) and also a script to do solderpaste scaling.
[quote author="oliver"]Edit: Btw, I only increased the diameter of the U2 to match all the other parts, so those are the default rings etc sizes, so they should be 'alright'? Anyway, as I said, will never use mil grids or spacing but focus solely on metric scales. Tom sounds like a smart man![/quote]
As far as I could see, there is plenty of room for increased annular rings. You say you want to use 7mil spacing, but then use 10mil traces. Using 0.2mm (or 8mil) should give you plenty of wiggle-room on the board. Designing a PCB can be a fun puzzle ;-)
When using PCB in metric mode, you are advised to recreate most, if not all, footprints you use in metric dimensions. The default footprints are all based in mils and that mixes very badly (I can tell, tried it and failed).
The PCB does not pass DRC checks. I get 56 errors with "copper areas too close". They are all under 8mil spaced. Do you have made the parts in 0.2mm design and not adjusted the DRC parameters (there is a 0.032mm difference 7.87mil is 0.2mm)?
I also suggest that you change the copper annular ring of the solder pads where you have connectors on the board. 11mil annular ring is very small. The drill hole (38mil) will get scaled to 0.95 or 1mm. If it becomes 1mm, you are in trouble.
500kHz is a real pain, but you should be able to press 10MHz through the line if setup correctly and all is matched. I pressed 8MHz TTL CGA signals through 15..25m of cable with proper buffering and termination without a hitch.
Do you have released some information about your projects? Sounds interesting.[/quote]
Hm, no, the CGA stuff was a project I did about 20 years ago. The tech hasn't changed though. Other stuff is on my homepage (http://www.vagrearg.org).
I guess I should write an article about that like I did the decoupling article. It is actually quite an interesting subject to deal with "long" cables and how signals can bounce in all directions. Something that can be easily visualized. Let me think about that a few days; I'll probably will come up with something. And then make some time to write it down. Darn, need to move at light-speed to use a relativistic clock that makes time ;-)
I guess this sigal looks like this due slow flanks time, right?[/quote]
Not necessarily. The noise at the low level (cyan trace) is severe and you even have a glitch. That looks a bit like cross-talk between the clock and data lines. Definitely a sign of problems.
[quote author="michu"]
Quote
Are you sure that you have a stable power supply
I use a 500W ATX Power supply, I used this one for another project (128 Led Modules) without issues. But there I didn't had long interconnecting cables. However I'll check the power supply with my scope and check if the 12V are pulsate, thanks for this hint![/quote]
The problem is not the master PSU, but what you have locally. You can have a lot of noise on the buffer's supply, even with a rock stable master supply. The cables are your worst enemy. That is why I wrote about the bypassing and the ferrite bead placed locally.
You should have the probe on the local Vcc/GND pins (at the 5V part) and see what it shows there (use only one scope trace with a floating setup). The buffers are sourcing and sinking a lot of current (probably > 100mA).
[quote author="michu"] The SPI clock is quite important yes, currently I use 0.5MHz. If I double that the error rate increases significant, I think I'll lower that to 250kHz. So, my next concrete steps will be a) recheck the Power supply and b) lower SPI clock rate.[/quote]
500kHz is a real pain, but you should be able to press 10MHz through the line if setup correctly and all is matched. I pressed 8MHz TTL CGA signals through 15..25m of cable with proper buffering and termination without a hitch.
[quote author="arhi"]I seen these modules in a strip 60m long and they work perfectly ... the distance between modules was short (<5cm) but it shows that delay ain't a problem ..[/quote]
That should be no problem with 5cm. The capacitive loading is low. However, introducing 5m of cable can make a hell.
One simple test is to reduce the SPI clock to a low frequency (say 1..10kHz) and see if that helps. That would allow the signals to settle before being sampled.
I've attached an image of the line-driver and termination setup. It doesn't matter too much if you use inverting or non-inverting drivers. However, inverting types have traditionally been faster and with higher drive force, but that is probably not true anymore with the newer families. I've also seen alternating inverting/non-inverting setups which can compensate differences in the high-to-low vs low-to-high transitions a bit better.
If this does not work for you, then the alternative is to use balanced differential drivers (or even low-voltage balanced lines (like LVDS systems)). That means that each output-line has an inverting and non-inverting output, which are both used at the input to reshape the signal. However, in a balanced setup it becomes even more important to do termination at the correct impedance.
Wow, that is some noise you have there. Are you sure that you have a stable power supply to the drivers with proper decoupling? If the power supply is unstable, anything can happen. Take the scope-probe and measure the power supply directly on the buffer's power pins and see what that gives.
The driver circuit needs to be put at the cable start. The driver is supposed to deliver the energy onto the cable. From the scope picture it seems that you are loading a significant capacitive load.
On the input side (the end of the cable) you normally put a Schitt-trigger buffer. This is to reshape the flanks/edges of the signal, as logic circuits are very sensitive to rise-/fall-time of the input. The termination resistors (plural) are put at the input of the Schmitt-trigger in a voltage divider setup. The voltage divider should have a tap-voltage that is in the middle of the Vth/Vtl thresholds. The termination impedance (as seen on the line) is the the parallel combination of the resistors (it is seen as AC and you must therefore have a low-impedance (local) power supply). You can experiment with the termination values. F.ex. 330/220 resistors provide standard TTL compatible impedance of 132 Ohm (330 to Vcc and 220 to ground) and have a tap voltage of 2V at 5V power supply (which is about where the Schmitt-tigger has its threshold; see datasheet for details). The termination impedance should be compatible with the cable impedance, but 132 Ohm is a good start.
Daisy-chaining many of these buffers will give you a significant problem due to signal degradation. The high/low times will shift because the Tplh and Tphl (low-high and high-low propagation delays) are not equal. This is not only due to the buffer's Tplh and Tphl differences, but mainly because the cable is not symmetrically loaded. Therefore, you should use the schmitt-tigger approach, where the line is pre-set at the middle of the threshold voltages. That way you will have about the same time for low-to-high and high-to-low transitions. You are running at a reasonable high frequency (>=200kHz from your image), so you are in serious trouble on the clock-line quite fast without reshaping symmetry.
If you use both MOSI and MISO in the daisy-chain, then you must route them in the same direction. This is because the clock will be phase shifted from input to output for each module and cable. If you are too far away in the chain, then you require two SPI interfaces on your CPU. One as master to provide the clock and one as slave to read the data. The slave's clock is the daisy-chained output. Your physical setup dictates how far you are pushing the envelope.
