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Messages - alanh

16
Project development, ideas, and suggestions / Re: mp3 player - mp3 decoder chip
There are numerous reference mp3 decoder implementations in HDL if you're interested in that route.  Could add a small FPGA (3E, XO2, etc) to do it and expand your I/O at the same time.  They might be a bit flakey, but if you are controlling the encoding of the source, they should perform well enough.
18
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
I'm not sure.  I happened on both the PCjr and Tandy 1000.  Two similar machines.  I suspect it could happen on others.

It isn't memory mapped related.  The PC should present any data on the data lines before asserting write strobes.  The propagation delay through a vintage '245/'245 isn't more than a couple nanoseconds tops.  But with modern logic, it's enough.

Oddly, it is an IBM machine that has an incompatibility with what would become the IBM industry standard architecture. :)
19
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
I have been fighting race conditions on my PLD design.  I have two more compatibility issues to diagnose this weekend.  Most of the problem centers around time shift between the read latches hitting and the read strobe rising.  Essentially this design (existing XT-IDE) tries to latch in the data using the same signaling that is telling the drive not to present it anymore.  The latch strobes really should be qualified against another time source - or a shifted time source.

I've also hit an issue where writes were too fast.  Some older PCs have extra buffers on the data lines and not the control lines.  The write strobe is dropping before the data is present.  I've had to qualify the write strobe with the bus clock to get extra delay.  Though that's a machine compatibility problem rather than a drive.

Some of the issues may require looping the signal a few times through extra cells to create some delay.  And I'm running out of cells on a 128 MC part.
20
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
The entire family of devices, 29c, 39sf, and others, have a standard way of reporting vendor and device ID.  It pre-dates CFI and there is no direct capacity reporting.  However if you have a populated datastore of IDs, you can determine the flash capacity in software.  My flash utility for the PLD IDE board does that for the more common vendors (SST - now Microchip, Greenliant, Atmel, ST, Catalyst - now ON Semi).  I know of other manufacturer codes for AMD, MXIC, and Fujitsu but not of the specific device codes.

The flash parts, while not exact, are very close to JEDEC pin-outs.  Only the upper address assignments are different.  The changes are small enough that I originally co-layed out my board for stacked sockets (offset 200 mills) for both Atmel EEPROM and boot flash parts.  After debating it a lot though, I dropped support for the EEPROM to open up some ground path.

EEPROM Pros:
 - Many people have JEDEC compatible 28-pin parts already
EEPROM Cons:
 - Smaller capacity (Universal IDE BIOS guys are requesting 16KB)

Flash Pros:
 - Cheaper / more readily available from distributors
Flash Cons:
 - A path to accessing at least 32KB through direct map or window must be designed for in-circuit programming

But as I mentioned, the pin-outs are close enough that you can stack the sockets offset and do both.
22
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
The Atmel PLD design is a nearly direct extraction from the PCjr IDE board that has been testing for a long time now over three spins.  I just ordered a limited PCB run of it this past weekend.  It has 1MB RAM, 512KB flash, IDE, RTC, and POST display.  The ISA board just takes the IDE & Flash parts of the design.

I'm ordering a first spin of a new ISA card this weekend.  One that adds 32MB SDRAM and a Cortex M3 with high speed USB host - based around Lattice's new MachXO2 line.
23
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
The Atmel design is working on test boards but with a potential gate racing condition that is causing some compatibility issues with specific drive models.  I'm gathering more info on it so I can tweak the PLD code.  It's the last gate before what would have been a 50 board run.  Now depending on how this turns out, it might be a dead project.  It already supports memory mapped operation and the resulting speed benefits.  This board has the same potential but without the additional ROM capacity.  Future plans included using the 496 KB extra space as a ROM disk to store your OS independent of a drive (and very fast!)

I would fully embrace this project but I'm just not crazy about 3.3V or SMT for hobbyists.  DP is in a unique position with Seeed so it eliminates the last concern.  I still think there may be issues with drive current.  Has anyone looked at the actual draw through the regulator?  Or a simple touch/heat test?
24
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
You don't have to expand it to 32KB.  You could make it as small as you want as long as you have an additional pannable window.  My Atmel CPLD card I use a 512KB flash part.  I have a 16KB window for the option ROM select-able by DIP switch.  And a separate 8KB pannable window that can be enabled/disabled and re-positioned in main memory via software.  I can program the whole flash part just fine.

All my design files are on a public svn at http://www.retrotronics.org/svn/jride/trunk

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