That is a cut down version of the JR-IDE board which I have running at home. It's the same IDE related sub-set of the circuit just moved to an ISA form board and card edge with pins reassigned for routing ease. I like it because the BOM count and total kit price is very low.
My target this weekend is have DOS booting off the HD by Sunday. I'm chasing some other problems with some of the extra features on the JR-IDE version that are slowing me down. And I'm attempting to at least re-write a basic BIOS in Watcom C so it's more maintainable by more people yet still as efficient as the Universal XT-IDE BIOS 1.15. My tentative schedule is to finish prove-out this weekend, make board changes during this upcoming week, and send P2 of JR-IDE and P1 of the board above to fab (Dorkbot PDX) by next weekend.
The 100 will have a few unbonded pins. There is also a 5 volt 84 pin J-lead variant. It's more expensive, but not by much when you include the cost of the LDO and buffer.
You could use the non-XL chip variant, but it's about 2x the cost for a J-lead part and 3x the cost for a flat pack. But it saves buffers and the LDO reducing your BOM item and line count.
[quote author="FoolDupleX"]You may start with the D0-D15 lines on the IDE connector. D0 for example. Even if this is not the true reason for the problem you observed, it si always good to have an idea of the quality of the signals. It has a direct influence on the speed that can be achieved reliably.[/quote]
Annex C of the ATA-4 spec sheds a lot of light on this. I would think at an effective transition rate of no more than 200-300 KHz, signal conditioning shouldn't be necessary.
Icurrently have an ISA card with a large CPLD (2k luts) and a small FPGA (5k luts) connected to it - along with 3 4MB SPI flashes, 32MB SDR SDRAM, 1MB SRAM, 2 RS-232 drivers, a Super I/O chip via LPC, RTC, a FTDI VNC2 w/ 2 OTB USB ports, temp sensor, eeprom, and a whole host of other goodies. It's the perfect test bed for PC/ISA proof of concepts. But my focus right now is JR-IDE which closely parallels this effort. I'd be nice to cooperate on some of this instead of duplicating effort as my next project is a 32 MB ISA Conventional/EMS/XMS/ROM board (P1 spin hopefully early next month).
As far as this project, my overall concern is cost and assembly-ability.. if that's a word. The CPLD version can be the coolest thing in the world, but if the cumulative component costs get too high, it dampens the enthusiasm. I used the Atmel parts because they are 1/3rd to 1/8th the cost of equivalent XC9572s (don't even get me started on Altera). I also used 39SF0x0 flash parts since they are generally cheaper and more available than equivalent 27xx or 28xx [ee]PROMs.
XC9572s are fine though. The high price may be worth it if the project serves as a gate way for more people getting turned on to HDL and standard tools like ISE, Quartus II and Diamond. Atmel is stingy with Prochip Designer licenses and WinCUPL is a steaming pile of sh*t but at least free.
I would also recommend changing the JTAG header to match one of the many many parallel port programming cables in eBay with a 2x5 .1" header. People can buy them assembled and shipped from Asia for under $15.
And in a clean two IC and 1 header or CF slot design, I still don't understand the preference towards SMT when everything is available through hole.
The way I went about it on the JR-IDE, was to shift the address lines up in code A3..1 -> IDE_A2..0. The latches are contained within the PLD. A read from an even address activates the appropriate IDE CS (based on A4) and returns the lower IDE lines on the ISA data lines and a common 8-bit latch grabs the uppers. An odd read returns the latch values. That way 8-bit reads and 16-bit reads function the same and correctly. Natural IDE register ordering is preserved (only the x86 address offsets get multiplied by 2). This basically what Chuck intended but it was easier just to rework two wires and reorder the register offsets in code.
ATM for writes, writes to even addresses go to the same common latch only. Writes to odd addresses activate the appropriate IDE CS (again based on A4) and present the ISA address lines on the upper IDE bus data lines and the latch contents on the lower.
I currently have all writes working this way as I'm running out of cells. The JR-IDE does much more than just IDE and I'm using a rather small PLD. However the above behavior could easily be restricted to just the data register (A4..1 = b'0000) and writes to other registers could happen directly with either a non-deterministic upper IDE byte or zeros. The current method isn't that bad as adding an extra bus cycle for setting things like the sector address is a small price for the extra benefit to sector loads.
The IDE registers are also memory mapped on the JR-IDE board. Though that may be moot since I believe most PC clones add the same waits for 8-bit memory as 8-bit I/O (not 100% sure though). I don't have an option BIOS fully written yet so I can't benchmark atm. That will hopefully happen next week as I'm currently working on a nice framework for OWC.
I'll post the CPLD code I'm using for all of the above later this evening once I get home from work.
