Do through-hole exist? Anyway, if it's rear facing (so that the card sticks out the back of the computer when it's in its slot, subject of course to getting a suitable bracket) then perhaps with-button. But if it were internal facing, effectively making an updated version of a hard-card, then probably without. IMO anyway :)
EDIT - I was looking at this one from Farnell, but it's not really clear to me whether its the entire socket and mechanism, or just the release mechanism to somehow add to a socket, as the picture looks nothing like the datasheet. Oh and it's about £2.
Re size limits, the issue there is in the running OS's most likley (and lack of CPU power to process large FAT partitions). I agree with the CF-poking-out-the-back, it would be great and mean one less power wire connector needed too. USB might add considerable complexity I'd guess, plus there would need to be some driver or similar to detect whatever was plugged in?
Do we have a wish-list for a v2 CPLD version? A v2 of the original is being tested it has been mentioned on VC forum, and one of the changes is to provide for a large EPROM (up to 32KB, i.e. 28C256). I don't know how much capacity the CPLD might have, but another thought that crossed my mind was whether dual-port would be an option. Obviously avoiding unnecessary complication will presumably be the goal, but I wondered how much can be implemented via CPLD code.., i.e. how much "minimal" hardware would be needed on the board to provide that option (i.e. a second 40-pin header).
Hi, I've posting a link to this thread over on vintage-computer.com forum, and there has been some useful input, Chuck suggesting, "If I had the luxury of a CPLD on board, I'd rework the read/write logic so that word I/O was transparently done to the drive without the loopy "Chuck mod", so that both reads and writes would be sped up".
So the A0/A3 address line switch is a simple-to-implement fix, but not the optimal configuration. The mod allows for 16-bit transfers via in ax,dx; stosw instead of byte transfers then xchg. But Chuck then explains (see here, post #43) "you can't do writes this way because the latch needs to be written before the IDE data port because the way the circuit is designed, it's the write to the even address (IDE data port) that triggers the data transfer to the IDE internal buffer. You could devise additional circuitry to fix this".
So maybe there is a bit of work to get this really optimised. I just wanted to raise this in case there is another iteration of the board, it would be great to get the design really optimised!
I believe the mod affects all the address lines on the original XT/IDE, as a modified (byte-swapped) version of the BIOS needs to be pushed onto the card prior to modding. Could this be made available by (yet another) set of jumpers?
Sorry just to add, IMO it would be great if the card had a bracket-facing compact-flash socket, if it could somehow be possible to have the mounting points for one as well as the 40-pin header (so the assembler could choose). I'm just asking - I don't know if that could work? I guess it would need a jumper somewhere to select master/slave also.
Absolutely awesome work! It's great news that the 3.3v board works... I don't know a 5V CPLD is needed, as the whole ISA bus is a 5V specification anyway, but the 3.3v works because it's all TTL driven. So my o-scope didn't lie it seems :)
Can you test the performance? I've wrriten a very simple little utility to do so - some numbers are on the page too (be sure to set buffers=99 in config.sys).
Thanks very much indeed for posting these links - very much appreciated. The board I have here is identical to that pictured above (Sep-2010 on bottom left)... this is a 5V board?
