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Messages - FoolDupleX

1
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
Eager to learn more. What puzzles me is that identifying the drive is technically like reading a sector on the hard disk: the IDENT command is sent and the disk returns a 512-byte buffer with the ident info. Reading a sector is : send the READ command and the disk returns a 512-byte buffer with the sector that was read. There's no difference at the interface level. So ??
2
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
100 uV should be fine at 3.3V with the "low" speeds we're talking about. I have made other designs based on Xilinx CPLD with the 1117 as the regulator for interfacing with old hardware and I have never noticed any issue concerning the noise.

What should we understand from your update from vc ? It looks like nothing works with the v2 or almost ?
3
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
As sleepwalker said, my concern was really about finding the regulator easily and at a low price. Ten years ago I used to source my components from Farnell or other similar distributors. Today, I order most of my stuff from ebay and as samples directly from the manufacturers when they offer this possibility. I spare the shipping costs + stupid "tax" for small volumes and it's WAY LESS expensive even per component.

Now about the consumption, heat and noise - I really think you worry a bit too much. I work a lot on reviving old computers (see here: http://http://www.memoires-informatiques.org/?en) and can tell you that a CPLD like the xilinx, even with thousands of gates, draws a lot less juice than a bunch of 74LS from the old days. Therefore, a lot less heat too. On the contrary, modern electronics, due to their incredible speed and low voltage, need LDO and low noise voltage supplies in order not to disturb signals. When I look at my oscilloscope plugged to old PCs from 20-30 years ago, I am confident that 100uV of noise won't be much of an issue :-) Crosstalk and impedance mismatch for example are much more of a concern to me when designing electronic circuits.

Electronic components today really can't be compared with those 30 years ago. Does anybody remember that a 5% tolerance for a resistor was considered just 20 years ago to be excellent ? Today, 1% is average quality, not more.
5
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
Indeed. That's mainly because the Vpp is +12V, which, again, is cumbersome.

Always looking for cheap easy-to-find second-hand components, I turned myself a few years ago to the 29C0x0 flash family which is functionally speaking very close to the 39SF. This family was very popular for BIOSes and embedded systems around 1995-2005. But the pin-out is slightly different from the 28C64, it's a 32-pin package, just like the 39SF. The programming is software-driven so you don't need any special programmer.

Using a big memory for storing only 8 KB of code is not a problem per se. In the end, only the cost matters. I've harvested lots of motherboards in the past ,looking for 29C0x0 chips so I've got plenty of them for free that's why my preference would go to them, but that's really personal. As with the 27C, I could provide some for prototyping.
6
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
Yes, I've seen that :-) While the 27Cxxx are just EPROM and therefore a bit painful to reprogram (UV light needed for erasure), they're rock-solid and very easy to find. I've got tons of them and may provide some for free. I agree however that they are cumbersome and I've myself turned to flash memories for my recent developments, such as the 29 family, but these start at 128 KB, which is a bit big for the xt-ide.
7
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
Hard to catch up when you don't have any spare time ... ok, I've just received my v2 PCB from Ian and am populating it. I've reviewed the schematics in Eagle and I've got a few questions/remarks that may have or may have not been discussed on this thread (please forgive me if they have).

- The values of R1 and R2 are missing ; I have assumed they are 10K, correct ?
- the value of R6 and R7 is not clear to me : 151 ohms ? strange value and isn't it a bit low to supply a LED with +5V ?
- a small enhancement of the pcb which would add more flexibility with the ROM: by connecting the unused pins of the 28C64 to the ground, other pin-compatible chips such as the 27C128 and 27C256 (which were very popular at some point) can be used as well.

I let the owner of the schematics make the modifications if needed.

That's all for now.
9
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
Just for info, I checked the official CompactFlash specification : "the CF shall operate at both 3.3V and 5V supply voltages. The current requirements shall not exceed 75 mA at 3.3V and 100 mA at 5V." Also, Vih on the I/Os is minimum 2.4V when VCC is 3.3V and 4V when VCC is 5V. Vil is respectively 0.6V and 0.8V. This may explain why the card does not work properly when it is powered at 5V if some of the I/Os connected to the Xilinx top at 3.3V.

Being familiar with the XC9572XL, I've always measured outputs around 3.2-3.3V. I guess the 2.4V specification is a lower bound when the component is under heavy load.
12
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
Quote
Annex C of the ATA-4 spec sheds a lot of light on this. I would think at an effective transition rate of no more than 200-300 KHz, signal conditioning shouldn't be necessary.

I agree with that, however my concern is not jitter but crosstalk, whose existence depends on the design of the PCB and which can induce glitches on the bus.

I don't think the XT-IDE on CPLD as it is right now is very expensive and the reliability/debugging easiness/flexibility in comparison to a bunch of 74s are much higher.

SMTs are not a problem. I solder TQFP-100 regularly with no special equipment. It's a matter of technique and not being afraid of SMTs (I used to prefer DILs). I agree however on the flash, I've always been a bit reluctant with the bulky E2proms.

Anyway, I think we should not overdiversify. v 1.1b is already quite fine and should be finished before we tackle v2.0 and if there's indeed a problem with the cross-talk, better get rid of this now before adding complexity and features. A simple oscilloscope probing will tell us if we can simply rule out this hypothesis or not.
13
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
You may start with the D0-D15 lines on the IDE connector. D0 for example. Even if this is not the true reason for the problem you observed, it si always good to have an idea of the quality of the signals. It has a direct influence on the speed that can be achieved reliably.
14
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
This definitely needs investigation ... the CF standard specifies that CFs must be able to work at both 5V and 3.3V levels. The 74 buffers deliver signals at 5V. If the CF is powered at 3.3V, the signals should be 3.3V. Why it works better with this apparent incompatibility eludes me. Maybe there is a problem with the levels, the transitions or some crosstalk occuring between the lines on the card which impedes communication at 5V but is negligeable when the CF expects signals at 3.3V. It may also explain some apparent incompatibilities with some hard drives. Since the lines are not terminated on the card (no RC couple to mitigate cross-talk and reflection), it's a possibility.

Is any of you able to stick an oscilloscope to the card ? I have the oscilloscope but not a working XT-IDE card ...
15
Project development, ideas, and suggestions / Re: XT-IDE adapter with CPLD builds
This poll is a nice idea. While I like the idea of mimicking a hard disk with the network, I think it is out of scope of the project. USB on a PC-XT for mass storage is utopic : I am presently working on a USB interface for a french 8 bit computer similar to the C64 and while low speed is very easy to achieve (keyboards, mice), full speed is a nightmare due to extremely short timings (the devices simply time out and often reject the enumeration).

I have also developed a CF interface for my french 8 bit computer and I have quite some knowledge about CFs. The issues with modern CFs are related to the metaconfiguration of the card, which is not quite achievable through the ATA interface itself. But I managed to make 4 and 8 GB CFs work on my machine (my interface does not use ATA but direct memory mapping). Using all kinds of CFs on the XT-IDE would mean adding an extra software configuration step at boot time and a bit of electronics, not much, to access the extra registers of the CF and configure an ATA mode compatible with the XT-IDE. Which is certainly achievable with a bigger CPLD.

My original goal, before discovering the XT-IDE project was to design a hardcard to replace the one I have (A WD Filecard with 20MB) which has been running fine for 25 years now (not a single bad sector). It's just perfect, except for its capacity.  A 2 GB 2"5 hard disk is a few bucks on ebay, so with the XT-IDE, this will perfectly fit my needs.

nb. I am pretty confident that when the 2 GB hard disk will have worn off, the WD Filecard will still be operational ;-)

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