1
Bus Blaster JTAG debugger / Re: Where to get v3 buffer logic SVF files?
Wiring scheme follows: suggestions/corrections welcome.
Code: [Select]
A20 User Manual / Full Name / FEX Line (linux-sunxi)
PB14_SELECT 011 (mux 3) = JTAG_MS0 / JTAG Test Mode Select (TMS) / jtag_ms = port:PB14<3><default>
PB15_SELECT 011 (mux 3) = JTAG_CK0 / JTAG Test Clock (TCK) / jtag_ck = port:PB15<3><default>
PB16_SELECT 011 (mux 3) = JTAG_DO0 / JTAG Test Data Output (TDO) / jtag_do = port:PB16<3><default>
PB17_SELECT 011 (mux 3) = JTAG_DI0 / JTAG Test Data Input (TDI) / jtag_di = port:PB17<3><default>
Voltage target (VTG, input)
Bi-directional reset (TSRST, inout)
Signal / Bus Blaster JTAG Header / LIME2 (Rev. B) GPIO-3 Pin
TMS / 07 (TMS) / 26 (JTAG_MS0)
TCK / 09 (TCK) / 28 (JTAG_CK0)
TDO / 13 (TDO) / 30 (JTAG_DO0)
TDI / 05 (TDI) / 32 (JTAG_DI0)
VTG / 02 (VTG) / 03 (3.3V)
TSRST / 15 (TSRST) / 05 (RESET#)
GND / 04 (GND) / 02 (GND)
BB JP4: 3.3V->Target: Open
Digikey # SAM8665-ND + CSR20G-ND; all lines less than 2 inches long, no additional caps/resistors added