What are people's favorite BLE modules? I have been out of the game for a while.
Looks like there are plenty of slave modules but it would be better to not need a second microcontroller as most run a Cortex Mx or similar inside anyway.
Best for me if it is already FCC or similar certified. I have found a few and am digging now but the software stack use with custom firmware seems a bit muddled on everything I have found so far.
Does anyone know off hand what if any packets a phone associated with some wifi network sends if it does not hear a beacon? Some SSIDs are not broadcast so it might send something even before it hears the router/base stasion. I've started to look but have found out yet... If anyone knows it will save me much hunting.
It sounds as you would expect very very good. I had a minor issue with a capacitor being of the wrong type and the THD was higher until I noticed I put in the wrong kind (not by much but some) but because this design is better than my amplifier (or my ears) I honestly didn't hear the difference, I could however see the difference in the objective measurements immediately.
The design is essentially complete and tested as of 7/12/2015. Software and hardware are fully functional.
A kickstarter may be launched if there is large interest. The full design will be open source at the end of the project. I want to give it one more update to try to improve the right channel performance and do more to filter high ripple power supplies.
As of 7/12/2015 only intermodulation tests still need to be performed. Given the other results it is highly likely they will be similar to the ODAC.
Tests were performed with an Audio Precision System 1 (SYS-222G) with 24 bit files at 44.1 KHz.
A typical spectra for the DAC driven by the BBB at 1 KHz -1 dbFS is shown below:
Here there are plenty of harmonics, but these are due to the dynamic range of the converter circuits in the AP-1 interface. The notched path shows the true signal components, note the change in the y-scale:
As we can see here the spectra is very clean. The change from a cascade of LDOs to a single very low noise LDO has improved the noise floor and with it the THD figure. Here is is < 0.003%. This is the left channel of the DAC. The right channel shows a larger first harmonic signal the reason for this is not obvious from the board layout but will be investigated in the future.
Also of interest is the flatness of the frequency response (at -1 dbFS):
The flatness is essentially +/- 0.1 dB exactly the same as the ODAC. It is actually louder than the specification at low frequency. Here 0 dbFS = 1.9 V as the design is being run presently at 3.3 V rather than the 3.6 V of the ODAC.
Along with the sweep of the frequency response, a sweep of the THD can be done using the voltmeter inside the AP SYS-1 after the notch filter:
As can be seen the right channel is higher than the left. Inspection of the spectra show that it is largely due to a higher first harmonic distortion component. Further study of this may be needed to understand the source. I note however that although this is a mystery it is still a very low distortion number and already better than the amplifier that I own (thus transparent).
The left channel starts at 0.0035% with a minimum of 0.0024% and peaks at 0.0048%. The right channel starts at 0.0051% with a minimum of 0.0043% and peaks at 0.0058%.
The dynamic range at -60 dBFS was also measured, here it is plotted notched with A-weighting applied.
With A-Weighting the dynamic range is 104.8 dB. This is greater than 16-bits (96 dB), and thus more than my goal since the vast majority of audio sources are derived from Redbook audio.
Theoretically 112 dB is possible for this figure, the ODAC got to 111 dB with whatever USB power source the creator had. This figure will depend on the power supply used and is part of the reason I have added a TODO item to improve the power filtering.
Crosstalk is well controlled at 10 KHz:
The datasheet says we should get 100 dB and that's essentially the result. The actual figure is 99 dB at -1 dbFS, so the figure is isolation is 98 dB. More than enough.
THD at 0 dbFS at 100 Hz was also measured. No increase in distortion was observed with the current design.
This design is essentially transparent for minimal cost and usable directly with a BBB. The primary cost is the milled aluminum case.
I got all the software running nicely. Now I'm back to hardware. Couple little things, they all have little fixes I can do without getting new PCBs, so I should be ready with all the results by July 12th I'd guess if not a bit before. Things look generally good though, nothing show stopping yet.
I got new PCBs but there was a geometric mistake in the placement of the power jack so I had to order new ones. A few more weeks before new results because of this error.
So... I am moving across the country for a new job. Things are rather busy here as a result, and things will be busy there as well for at least the first 6 months I should think.
This leaves not a lot of time to do this project! Eeep. Therefore, this weekend I redid the PCB in hopes of finishing the project to completion before my move.
I didn't have time to fully compare the isolated vs not-isolated variations but I did check that two different types of clocks were basically the same if used with the external USB I2S source. This isn't a 100% proof that I don't need to use the more expensive clocks because the USB I2S source has its own clock to generate 3 of the I2S signals and with the clock swapping only the MCLK is really being changed. However it is the best I can do, in the time I have.
I'm sure there has been progress on the drivers as well. There is milled Aluminum case this whole thing sits in as well. If I didn't mess up the geometry of the PCB any then it should all be ready in about 2-3 weeks to show what the final versions will look like.
In June hopefully I will put together the PCB and it will both fit and work. If so I will make as many measurements of the design as I can and make a determination if any further revision is warranted. I have time perhaps for 1 more generation of PCB before my move.
The PCB is laid out so that I can do isolated and non-isolated connections for the I2S bus. I made the following changes:
I changed the analog supply LDO to TPS7A49
I removed the cascading of the LT1963 and analog supply LDOs (this will reduce noise at the cost of lower PSRR in theory, see previous post)
I provided a direct connection the BBB from the DAC board, with a ground plane that will short to the case. This is microwave RF style to provide shielding from the BBB.
I switched to 0402 components for almost everything except large caps and the audio line out resistors. This allowed me to place everything almost on the package of the DAC (you can't do better than a 0 length trace, no matter how many ground planes there are).
I removed all electrolytic capacitors (polymer Al super low ESR) to improve device lifetime, etc. All caps will be NPO or X5R/X7R type.
As per my last post it is now April so I had a little time to do more work on this. Rebuilt the clock boards and stuck with the external I2S source for now.
No difference was seen between two very different cost clocks for MCLK. Now this would effectively use the DAC asynchronously and the other signals are all still from the same clock however its reasonable evidence that I need not spend money on the more expensive clocks for this design.
I switched to my simple wall DC supply from a bunch power supply and the 60 Hz noise is worse though I note as before that could be for other reasons. The numbers don't really add up properly given the amount of PSRR that should be available at 60 Hz.
I need to probably switch to BBB next and see if I can witness any difference with the two clock sets.
I think I mentioned that I have the cases so the next version of this will fit the cases and perhaps be the last PCB version if everything looks nice.
I just wanted to give an update that I expect to get back to this in March/April. I am sorry it has taken such a back seat, but I have machined cases for the design now. I am unfortunately traveling most of the rest of this month so there is no possibility of progress until March really.
The best one I have is based on CM6631A, I don't want this to be an advertisement for one or another though, just like companies do "competitor A" and B, I should. Because honestly a lot has to do with the clocks selected and the board design potentially. I note performance of this usb interface is bad when used with BBB or r-Pi as I recall. But was fine under Arch with a x86 laptop. All tests are windows for USB interfaces in general.
I should return to testing with the BBB soon. Now that I have absolutely clear spectra I can proceed to fix some issues. I already have decided to change the LDO config and bypassing somewhat on the next version of the board.
I might do some tests with the external clocks using the async mode with the external usb interface to understand the phase noise of the clock options if the phase noise like signature remains in the BBB output.
A quick follow on to my last post. The DAC board currently has a cascade of LDOs, this is bad for the noise floor by about 3 dB, but increases the PSRR. Total it in principle has over 130 dB of rejection at 60 Hz, therefore it seems highly likely the RCA cables are picking up 60 Hz from the room to this level. Since 74% is background it may be wiser to use a single LDO rather than the cascade. If I reduce the background noise floor by 1/2 and remove all the line noise that should increase the THD+N by 3 dB. There is also 1 dB left full scale. The 1st harmonic will probably increase 1 dB or more if measured at 0 dBFS. Still it seems reaching ODAC in terms of THD+N is could be very close at hand.
For those who are following this thread. I have new measurements. Hooray!
As I mentioned I have acquired an audio precision system one. I managed to get the GPIB model with DSP. Everything seems to be working but reading data is painfully slow for high resolution work (large numbers of FFT points). If there is a way to do a binary transfer with a single GPIB command I don't see it in the manual. So it goes at about 3 points a second. Not exactly speedy.
Nevertheless I had the time today to do some initial measurements with my modular DAC board. Since the best performance was with an external USB I2S interface I had in the last test that is where I decided to start to verify the integrity of the DAC PCB design and power supplies that supply it etc.
The results are more clear than using the Keithley.
Without the notch filter we see the limits of the converter in the AP Sys 1 unit in terms of THD.
With the notch filter on (taken at the same time but with the second channel) we see lower noise floor.
Calculating the THD+N over a bandwidth of 22 KHz the data suggests: >86.9 dB for 1 KHz @ -1 dbFS input (0.0045%)
This is below the maximum value (0.005-0.006%) in the ES9023 but above typical (0.002%). As can be seen from the data the primary issue is actually 60 Hz rejection. Followed by the first harmonic. The spike at 12 KHz I believe to be anomalous as it is present with no signal input.
Since the data falls within the tolerance for this measurement in the datasheet this is already acceptable, but I will explore the 60 Hz noise more before moving to two tone and other tests.
I also note of the residual THD+N contributions the the spectra is 20% line noise, 74% background noise floor, 5.5% first harmonic and 0.3% everything else. I will have to test the SYS-1 unit to see what its own background noise level is presently.
Once the DAC alone is fully verified I can return to the BBB tests and the mystery of the phase noise like signal spread.
