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Messages - d18c7db

2
Project logs / Re: Hybrid SID Player
Yes the FTDI can easily go up to 3mbits. That is the reason I was sort of asking what baud you were running your board at. I found out the limitation when I tried to play tunes with samples such as Isengard as in your video. It won't be hard at all to increase the baud rate. As for the buffering lag anything is possible with a bit more time and effort :)
4
Project logs / Re: Hybrid SID Player
No, I'm using a SID VHDL core with unknown attribution, I suspect it's possibly made by Kevin Horton at http://blog.kevtris.org and on his blog he states he implemented the filter externally to the FPGA in hardware.
5
Project logs / Re: Hybrid SID Player
Thanks Markus, that makes perfect sense, it didn't occur to me that serial would block. I imagined that ACID64 was sending data at a constant rate, which is was the rate to be played at.

Now you pointed me in the right direction, I spent some time this weekend and got some initial sounds out of my board. I'm using a Papilio FPGA board with a SID core written in VHDL. The sounds coming out sound 90% correct, the tunes are definitely recognizable :) but it's early days, I still need to fix a bunch of things.
6
Project logs / Re: Hybrid SID Player
So what baud rate are you running the serial port at then, just the standard 9600?

Basically, I run ACID64 playing ghosts'n'goblins (5.5Kb file) into your python server script modified to write to a file instead of sending the data out to serial. After 10 sec I ended up with a 3.8Mb file, hence ~ 380Kb/sec.
7
Project logs / Re: Hybrid SID Player
Markus, I imagine you have to run the USB serial port at about 4Mbits/sec in order to keep up with the 380Kb/sec data coming out of ACID64.
8
Open Bench Logic Sniffer / Re: RFID support
Hi, I'm fairly well involved in the Proxmark community and have looked into the Proxmark design in depth. I am currently in the process of redesigning it with slightly more updated hardware, the latest working prototype uses the same FPGA as your LA, an XC3S250E 100VQFP, and ADC08060 A/D amongst other changes.

The FPGA currently coded in verilog does the basic 14443 a and b RFID demodulation, however the rest of the protocol is handled in software on the ARM microcontroller (AT91SAM7 based). The good news is that the existing verilog code is trivial to port from the original proxmark Spartan2 FPGA to the new Spartan3 and I have in fact tested that it works in practice. The not so good news is that you need to either implement the further higher level protocol handling in the FPGA or add an external microcontroller (or maybe look at an FPGA soft core micro).

Since that video above was shot, the board was redesigned several times and the latest one should sport a touch pannel 320x240 LCD which remains to be tested, as it is attached to the FPGA pins and I have yet to write the verilog code to drive it.

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