Jack. Looks good to me, I wish you could have found room for the Res pads , I noticed the Dir pins on the buffer IC were not routed , I hope you plan to control them with the FPGA
re IPenguin remarks on the old thread: Let me reiterate the main idea is to add a little extra board space for depopulated options (<$.50). The base board would not include the 2nd tranceiver or termination resistors. The Resistor pads would be initially bridged. All the user would need to do, would be to use an Xacto to cut the bridges and add resistors of his/her choise. As to 1x18 etc or 2x9 configuration, with the 2x9 configuraton the user would purchase either 1 or2 probe cables since they would be identical. This keeps the base offering at a cheaper 8 probe cable. Ideally an addon kit would be availabe having the 2nd probe set and transceiver and maybe a few termination resistors. The same 2x9 header could be used on a future "wing" to provide 24 or 32 channels
Attached are the zip files for the 16 bit buffer option I proposed. note the following changes I moved the termination resistors to minimize the added board length. I slid inputs 1-9 down a pin on the FPGA to accomodate the direction control pin routing The input0-7 order has been reversed on the connections to the FPGA inputs 8-15 have been attached to the FPGA's pins 2-5 & 9-12 The direction control for port b was attached to FPGA pin 15. I wasn't sure if pin 13 (IP) could be used? Was it okay to use these pins for the second port?
I am not a FPGA expert so let me know if I screwed up the FPGA connections
The board is 4.4in long verses the original 3.65in but with a little effor it can be reduced Also we could use the SOP package which is .1in narrower
Here an image of the 16bit buffer version This board is 4.4in long verse 3.65in for the original. If this concept is accept by all I will work to shrink it a little
Attached are the zip files for the 16 bit buffer option note the following changes I moved the termination resistors to minimize the added board length. I slid inputs 1-9 down a pin on the FPGA to accomodate the direction control pin routing The input0-7 order has been reversed on the connections to the FPGA inputs 8-15 have been attached to the FPGA's pins 2-5 & 9-12 The direction control for port b was attached to FPGA pin 15. I wasn't sure if pin 13 (IP) could be used? Was it okay to use these pins for the second port?
I am not a FPGA expert so let me know if I screwed up the FPGA connections
I feel like I'm beating a dead horse, but let me kick the horse one last time and see if I can get it rise from the dead/
Although I really feel a single 16 bit tranceiver is well worth the additional cost I would like to suggest a compromize. That would be a)use 8bit transceirers, b) do the routing for 2 chips but depopulate to one in base offering. It would be great if enhanced versions are forth coming but I have seen too many projects dead end after the initial go. The additional buffer opens many possiblity, with only programing additions,external clocks,triggers,function generator. I don't like the use of a latch where a bi-directional tranceiver culd be used just as well. I took a stab at the incorporation of the second chip to see if the roouting would be a nightmare, but it looks straight forward. Take a look at my snapshot.
I would be more than happy to donate my effort to contribe this portion, if Jack is pressed for time.
As to the termination resistors, from my experience they are highly desireable, again a cheap addition. I don't think a detail analysis is needed from my years experience a 22ohm will solve most ringing. If you really think its necessary to save pennies leave the pads and add bridges that can be cut. If you add the pads now the user has the option without requiring exspensive probes or clugging up a solution.
Sorry to be a pain, but I think it is best to bring up these issues while it easy to take care of..
I have asked the question before but didn't get an answer:
What happened to the use of •M74LCX16245 16 Bit buffers.? The M74lcx16245 was a bidirectional buffer where as the 74lvtx573 is a latch, I don't recall a discussion on why a latch was required Note 74LCX245 is an 8 bit version altough the savings are small
It seems to me using the 74LCX16245MEA, that 16 bits could be incorporated for a few pennies more. Mouser quotes 74LCX16245@$.654 verse 74HC573D @$.174 As for the additional header I suggest using a stackd one like the USBee uses.
What happened to the use of •M74LCX16245 16 Bit buffers.? The M74lcx16245 was a bidirectional buffer where as th 74lvtx573 is a Latch, I don't recacll a discussion on why a latch was required Note 74LCX245 is an 8 bit version altough the savings are small
If still planning to support 100mhtz, I suggest adding 22ohm serial termination resistors as was mentioned in an earilier post/
A suggestion, Ian, how about checking with SEEED about cases they migh be able to supply for the LA. This might influence the exact PCB dimensions. I would hate to have to use a larger case, when a small adjustment now would solve the issue. I agree 100% with the idea of minimizing the cost of the base LA. If I understand the present design, the buffered I/Os have been scaled back from the original 16 to 8. Might I suggest that the base PCB be layed out for 16 channels but depopulated to 8 for the base offering( no chips / header). The cost impact on the PCB I would guess be negligible. In Ian's latest post I think there is room if the buffer IC are slide up a bit .