[quote author="ian"] Sorry, hit post instead of preview. Here's a PNG of the PCB as it is now. I changed the name of the PCB to a, there was a good reason but I forget now. [/quote] Looks nice. Are this 16Bit Connectors? If yes, you may be a little short on ground and power Pins. Another nice addition addition would be an I2C or SPI bus on the probe connector. Then one could build a software controlled power supply for the buffer board. This way you could change the I/O voltage of the translator chip from the analyzer software. But you could always do this with a jumper on the buffer board or get the voltage from the target board.
If you are still using the AT45DB021D there are two variants of the chip, one 0.150" wide and the other 0.209 wide. One could make a footprint with longer [s:]pins[/s:] pads that would accommodate both.
[quote author="ian"] Great propagation delay on the NL27WZ126, wish it came in a 16bit version. [/quote] For a logic analyzer the propagation delay is a meaningless number. If you use one buffer chip the difference in delay between bits is usually to small to matter, a constant delay in the chip does not distort the measurement. If you must use more than chip the difference between minimum and maximum delay generates the errors, since bits on different buffers that change at the same time seem to change on different times. Another relevant parameter is the difference between rise and fall time in the buffer which should also be small.
My main reason for external buffers was other logic standards than 3.3V and 5.0V. For 3.3V and 5.0V an 3.3V Buffer with 5.0 V tolerant I/O would suffice. But newer logic ( e.g. FPGA and CPLD ) has increasingly 2.5V or even 1.8V logic levels which we could not sample with such a simple buffer even if the signal was slow enough. So the minimum necessary even with on board buffers is that the power supply for the ( onboard ) buffers is on the probe connector. This way the user can build their own buffer / level translator boards if they need them. But in any case it should be either no onboard buffers or buffers for all 32 channel. You could always populate only half for cost reasons.
I'm leaning against buffering the extra signals. It's possible to have an alternate upload for the FPGA that places these signals on some of the buffered pins, but having them unbuffered by default gives the cleanest, fastest signal path.
[/quote] How about an external buffer. This would require a second small pcb with the Buffer ( or level translator ). It should not be that expensive, because of the small size of the required pcb. It would also allow a longer cable between buffer and analyzer. I know that you don't need long data cables if you can put the analyzer near the target. But this would also allow to substitute the buffer pcb with a level translator pcb if the logic on the target requires this.
