16
Bus Pirate Support / Re: Circuit insight anyone?
Klaus Leiss
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Messages - LeissKG
Klaus Leiss
17
Bus Pirate Support / Re: Trouble using bit bang mode with 1-wire protocol
6. I need to send a matchrom signal (0x55) followed by the 8-byte address, then the start conversion command (0x44). I send the bulkwrite command in front of these like so: 0x19 0x55 0x28 0xa8 0xcd 0x5e 0x02 0x00 0x00 0xaf 0x44. I get back a six 0x01.
7 I then need to read the temp so I send 0xbe instead of 0xhh at the end: 0x19 0x55 0x28 0xa8 0xcd 0x5e 0x02 0x00 0x00 0xaf 0xbe.
No dice. I get a string of 0x01 back again.
[/quote]
I have not tried this but according to page 18 of the 18B20 data sheet you need a reset command between your start conversion and read scratchpad command. You have to follow that with nine read byte commands to read the scratchpad area of the 18B20.
Klaus Leiss
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OpenOCD JTAG / Re: First port of OpenOCD firmware to Bus Pirate
Use whatever is easiest for you, I won't stress about it.
[/quote]
If I remember the svn manual correct there is a server setting for this. Set eol-style to native and the
server will ensure that the repository has consistent line endings.
Klaus Leiss
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Bus Pirate Support / Re: BP v3 Arrived
I had another thought. I hindsight I was lucky to have more than one board so I could compare the defective to others. But without this I would have had
more problems since I probably had no hint when to check for the function of the mode LED. The self test guide in the Buspirate manual is also a bit
outdated. This could be a problem for others trying to test a buspirate.
Klaus Leiss
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Bus Pirate Support / Re: BP v3 Arrived
LeissKG - I'm really sorry about the broken LED. 1-of-3 is an really bad failure rate. Thank you for reporting that it was fixable, hopefully that also works for others with a broken LED. I'm glad you were able to get it going with some extra solder, but it's still really unfortunate.
[/quote]
No worry. If the failure rate were really 1-of-3 it would be bad, but until now it seems a lot lower lower. The contacts looked as when the solder did not
properly reflow. That means either dirty contacts or an incorrect heat profile. But since there is another LED in an identical package without the
problems the heat profile seems an improbable cause.
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I've made some changes to the PCB, firmware self-test, and QC procedure to help ensure this doesn't happen on future Bus Pirates, and Seeed has changes LED suppliers. I'll post a bit more about this when the new measures are completed.QC should have been able to catch this, but I have also seen enough products with teething problems during production ramp up to feel concerned about
the overall quality the boards. After if fixed the error on my third board I did a visual inspection of the boards and could not find any other obvious
problems with soldering. The overall quality seems quite good.
Klaus Leiss
21
Open Bench Logic Sniffer / Re: Digital Sampling Oscilloscope attachment (DSO wing)
this project seems another great ideia.
[/quote]
I concur it is a great idea.
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but why would we aim for such high signals? why not lower the costs or maybe trnafer the costs to more hardware that could provide more functionalities even thought with lower bandwidth?I don't think this are high signals. A 10 to 20 MHz scope is at the lower end of usefulness. And the parts are not that expensive. You can get an
200 MSPS ADC ( e.g. ADC08200CIMT) for around $10.
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why not a spectrum analyser (hardware assisted)?A lot of the spectrum analyser functionality is basically a scope plus software. But this would normally require a deeper buffer.
Quote
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Bus Pirate Support / Re: BP v3 Arrived
I updated and tested them today. Two had no problems and on one the mode LED did not
work. In this case it was a bad solder joint. After reworking the connections the third was
also OK. You can look at a picture off the solder joint in one off the attached pictures.
Klaus Leiss
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Open Bench Logic Sniffer / Re: Digital Sampling Oscilloscope attachment (DSO wing)
100 MSPS A/D converter ( I am not sure that sample rate is achievable without problems )
20MHz Analog frontend ( This is to high for the sample rate above, but you can at least check if the usual microcontroller oscillators swing).
1 to 20V input stage ( in 5 or more steps )
As Luke mentioned the buffer depth is not great but I can remember fancy Tektronix scopes with less buffer memory. I also think in Luke's
calculation is off. I get 120us at 50MSPS until the buffer is full.
Klaus Leiss
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Open Bench Logic Sniffer / Re: Digital Sampling Oscilloscope attachment (DSO wing)
This is a new topic to discuss a digital sampling oscilloscope 'wing' that will attach to the extra 16bit header on the SUMP PUMP.
[/quote]
Even if it is a wing, would you consider rotating the connector 180 degrees. This may make the pcb stack more compact. You may
obscure some connectors on the sump pump pcb but I think they are either normally not needed during measurement or useful on
the extension board like clock and trigger. This way you could build a cross trigger feature ( scope triggers LA or vice versa ).
Some relevant information for an Input stage can be found at
http://www.ssalewski.de/DSO.html.en
and
http://www.ssalewski.de/DAD.html.en
Another question is do you really mean 50MHz and not 50MSPS? I think for a 50MHz design you need between 250 to 500 MSPS. For that sample
rate you don have enough pins on the connector. Most fast A/D subsystem that I know of have either an fast A/D with an on chip demux or like the
Rigol scope a group of slower A/D that have phase shifted sample clocks.
National has also fast A/D, have a look at
http://www.national.com/analog/adc/eval ... _speed_adc
Klaus Leiss
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Open Bench Logic Sniffer / Re: PCB design
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Open Bench Logic Sniffer / Re: Parts list (rough design, options)
*Added PROG_B pulldown jumper for manual ROM programming
[/quote]
If you connect your programmer first and than set the jumper to programming you could get problems (BTDT). I would add two pins to the programming header, one for a ground pin and the other for PROG_B. A bridge in the connector would switch automatically to manual programming when you insert the connector.
Klaus Leiss
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Open Bench Logic Sniffer / Re: Parts list (rough design, options)
We can move the oscillator to any global clock input so we have flexibility there. What do you think about getting rid of the JTAG port? That would make routing over an unbroken ground plane much easier.
[/quote]
For the clocks I would suggest you follow the design note on page 59 of the data sheet.
Design Note
Avoid using global clock input GCLK1 as it is always shared with the M2 mode select pin. Global clock inputs GCLK0,
GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and GCLK15 have shared functionality in some configuration modes.
If I read Table 55 on page 80 right, the latter clock pins should be no problem in SPI configuration mode
Regarding the JTAG connector i would say omit it only if the design is otherwise impossible. If you have it, you can debug
the LA design inside the FPGA with chipscope if you have a license.
Klaus
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Open Bench Logic Sniffer / Re: Parts list (rough design, options)
Is there a clear or reset pin on the FPGA that the PIC can manipulate to hold the FPGA in reset while the PIC updates the ROM?
[/quote]
Pulling the PROG_B pin low tristates the FPGA pins. When it will go high again the FPGA starts its configuration. Figure 54 in the datasheet
describes how to connect an Atmel SPI prom for configuration. It also describes the standard programming header to program the SPI prom
with Impact and a Xilinx Jtag adapter.
[quote author="ian "]
I'd like 2 extra connections on the PIC->FPGA serial connection for a possible future update to faster SPI. Since the PIC, ROM, and FPGA already share an SPI connection, could we recycle the ROM connection for the UART/SPI connection? They'll never be in use at the same time, but there might be an issue with garbage data on the PIC UART while the ROM loads unless the FPGA indicates 'ready/loaded' on one of the other pins before we start the UART.
[/quote]
The Done pin indicates a successful configuration
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Open Bench Logic Sniffer / Re: Is the price a limiting factor?
Obviously the Saleae style is better if you want infinite samples, but many (myself included) don't see that as a requirement for a useful logic analyzer.
[/quote]
Infinite samples are sometimes useful, and this design could dump the data trough to the PC to get the same functionality. Depending on the data transfer speed of the used micro we could do this up to some sample rate and above that use the internal buffer memory. Another possibility is run length encoding of the buffer memory if the signals don't change as fast as the sampling rate.
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Open Bench Logic Sniffer / Re: Is the price a limiting factor?
The next should have more features.
Klaus Leiss