[quote author="arhi"]speed is not a problem, and the reason for both trigger and clk being in the sensitivity list is to have it async .. but maybe having it sync makes more sense[/quote] Yes, it makes more sense. Async designs will get you some time. Use only fully synchronous designs if you can. Regarding your original question, ISE should tell you if the routed design violates your timing constraints. You will have to have at least a constraint for your clock. Critical paths in your design can get their own constraints. See http://www.xilinx.com/itp/xilinx10/iseh ... raints.htm for a start. Setting a tighter constraint than you need can result in better routing results since the placer and router try to satisfy the constrains.
Note that obls has no external ram and that used fpga is not very big. Having more ram inside the obls or some ram on board (both things fairly expensive/unavailable if covering 200MHz parts that can be soldered by hand - so no BGA packages). [/quote] 200MHz would make it really complicated [quote author="arhi"] wrt extending obls (going with bigger fpga, ram on board etc etc) - the discussion is still open, but there is a huge question of BGA in hobby projects, also there's, as always, matter of price .. 50$ is cool price for a useful tool but if you pay 200-300$ for a tool then you start to expect "more" (support, software, development, stability ...) and to provide all that whoever is providing it have cost so then the 200-300$ item need to go to 400-600$ in order to cover the new cost and then the "hobby" side of it drops significantly. [/quote] A Version with more RAM should should not be that expensive. The MiniLa Project did a Logic Analyzer with a XC95288XL CPLD in a TQFP144 package and a 512Kx32 SRAM. http://www.mikrocontroller.net/articles ... ion_MockUp original project at See http://minila.sourceforge.net/ another Variant with an Coolrunner II http://coolla.freeunix.net/coolla.html
Unfortunately there is no continous supply of the minila. Sometimes somebody initiates a small build and then there is a gap
All prices below are from DigiKey.
The 512Kx36 SRAM (CY7C1381D-133AXC) costs $32 in singles, $26 from 25 on. A 256Kx36 SRAM is under $18, an 128Kx36 is under $10.
The OLS FPGA in a PQ208 package is $6 more than the PQ100. It is probably doable with an PQ144 that cost only $3 more than the PQ100.
You would also need a larger PCB that would also cost more lets say $20. It would be probably less
You can get 128K samples for $36 additional cost 256K samples for $44 additional cost 512K samples for $58 additional cost
I think this are the upper bounds for the additional cost.
I may totally wrong here, but i assume most of the overshoot is from the I part getting to big during the ramp up. I see two possible solutions for this, you either limit the I part or start the PID only if you are in a narrow window ( lets say 25 degrees ) around the desired temperature. Outside it , it is a simple on/off regulator.
A better way would to modify the core that unused channels are zeroed out at the input. A simple and gate between the inputs and a mask word would fix this problem.
This is basically the same as the miniLA or its derivative CoolLA. http://minila.sourceforge.net/ or http://coolla.freeunix.net/coolla.html I think it would be better to use an FPGA since the CPLD based device would only allow a very simple trigger logic. I think it is OK to build something that has a reduced feature set to learn something,. But if you want to make it a product I think there are already to much products on the market that could be vastly better for want of some small additional cost.
XC3S250E-4PQG208C ~ $15 at Digi-Key XC3S500E-4PQG208C ~ $20 at Digi-Key
the first should be OK but in case you will have an upgrade path. A PQ144 would probably also big enough but Digi-Key has only the XC3S250E-4TQG144C and not the XC3S500E-4VQG100C
Speaking of upgrades, is there a planned OLS with an XC3S500E instead of the XC3S250E? It has 66% more memory for a slightly larger price. 368640 Bit instead of 221184 Bits ( 40K to 24K)
[quote author="IPenguin"] - USB2.0 Development Board : ITDB01 (CY7C68013A-56 based) for $ 22 which comes with tons of examples (not just the standard Cypress examples) even explains how this board can be used as a JTAG programmer and debugger. [/quote] Additionally it is basically the circuit of the Saleae Logic Analyzer. It will probably be used as an Saleae clone like other CY7C68013A-56 Dev boards.
[quote author="ian"] Hum - did they buy from Seeed I wonder? I don't know anything about this. [/quote] It seems so. When you click on "Seed Studio" under the category Hersteller ( Manufacturer ) it is listed there.
[quote author="jack.gassett"] Yes, the pulldowns would be inside the FPGA and could be controlled through checkboxes or something from the client. I came across an example of using a Xilinx primitive to control the pulldown resistors from within VHDL the other day that should work for us. [/quote] For Xilinx devices this is usually done in the user constraints file ( *.ucf ). This file controls the physical layout of the device and the pin IO capabilities If you have a line like
Two back to back level translators should work. First translator goes from 3.3V USB device to 5V logic, the second translates 5V logic to any logic voltage between 1.2V and 5V ( for an Max3000 series translator).
I would use a 32 bit memory core and would add a demultiplexer with holding registers before the memory. With a 16 bit sample width you would write a 32 bit word to memory at every 2nd sample , and with 8 bit samples you would write a 32 bit word to memory at every 4th sample. For serial debugging you could do the same with 4 bit or 2 bit samples getting a still greater sample depth. This way most of the work would be done in the client software but i think at least for sample widths of 8 bit or larger no or only small modifications should be needed depending on the way the memory is read and transmitted to the client software.
[quote author="IPenguin"] After assembling an Arduino serial v2.0a, I realized that the serial arduinos don't use DTR to reset/start the bootloader ... the rest button must be pressed to activate the bootlaoder shortly befor downloading the sketch. Found no conflicts between the OLS/SUMP Java Client and an Arduino serial v2.0a/Arduino IDE r0018 when running both at the samme time. [/quote] You can add one capacitor to your board and it will reset on DTR like more modern Arduinos.
[quote author="sccs"] and again they are estimating the costs to be $60-$70 because apparently the parts used are expensive.
im more than happy to help out where i can. [/quote] Digi-Key has the FT2232HQ_MINI MOD for ~ $22. This is module with all parts the FT2232H needs. The FT2232H chip cost ~ $6 in single quantity. As Ian says the parts should not be more than $10 or $15 if including the pcb, provided the pcb order is large enough.
Maybe the higher speeds could use a baud rate auto adjust. This would require that after switching to this speed the user would send a repetition of known characters that have only two level changes. The pic could time this and calculate a prescaler value that fits this speed. If it receives at least n times the correct character after the prescaler adjustment it sends a prompt back so that the user knows the higher speed is now in effect.
