346
Bus Pirate Support / Re: Laser Cut Buss Pirate Case V3
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Messages - IPenguin
347
Project development, ideas, and suggestions / Re: Networked LED driver: rough design, options
- Serial communication (the cheapest ready available 3.3V UART/USB converters are the Nokia CA-42/DKU-5 compatible cables. You can get them from about € 2 /US$ 3 plus shipping - they work up to 115200 baud) ...
- USB Flash disk interface via FTDI VDRIVE2
- USB Flash disk interface plus MP3 playback via FTDI VMUSIC2
348
Open Bench Logic Sniffer / Re: PCB design
... the 4 signals Clk_In/Out and Trigger_In/Out are not placed awkwardly at all. The header is placed out of the way of the two I/O interfaces keeping the electrical design rather clean and giving even more options than "just" the Trigger_Out and Clk_Out signals on a header.Like LukeS, I like to use Trigger_Out and Clock_Out to take a close look at noise, glitches etc. you can't catch with the LA in circuitry before/after certain conditions are met. For this I will either keep a DSO running in continous loop-mode and stop it with the trigger signal (to look at a signal before the condition is met) or start the sampling with the trigger signal to look at it after the condition was met. Being lazy and to prevent errors when evaluating the results I use Clk_Out as a time reference when correlating the result on the DSO with the captured signals on the LA screen.
Clk_Out could be used as the Clk signal for the target circuitry as well. This allows to test the circuitry at different speeds while maintaining full syncronization with the LA without the need of an extra/external clock generator ... an other scenario is cascading two or even more SUMP LAs for situations that require more than 16/32 I/O channels. However, to take full advantage of this the existing SUMP LA client will have to be modified/extended ...
349
Open Bench Logic Sniffer / Re: PCB design
Honestly, I think for most users Trigger_Out and Clk_out will not be essential - they may never use them. The signals will be essential to those who want to cascade/syncronize the SUMP LA with (a second) SUMP LA(s) or other test equipment or syncronize with test circuitry/extensions. These features are usually found on professional LAs only ...
350
Open Bench Logic Sniffer / Re: PCB design
For the Clk_Out and Trigger_Out signals it's correct that those signals are not brought out to a header.
Unless Jack will go through the effort of routing them to the wing header they will have to be implemented in VHDL by using I/O signals on the wing header when needed ...
I will wait for Ian's and Jack's final say before updating the block diagram.
351
Web platform / Re: How do you program PICs?
I never developed with PICs before, I thought until a few days ago when I found a PIC Starter Kit (the one with a 40-pin DIL socket) hidden away in a rack that must be about 8 or 9 years old.
For Bus Pirate firmware updates/swaps I use the built-in bootloader and got a PICKIT3 a few days ago due to my interest in various Dangerous Prototypes projects.
352
Open Bench Logic Sniffer / Re: PCB design
Updated the block diagram to the latest PCB design release
353
Open Bench Logic Sniffer / Re: PCB design
354
Open Bench Logic Sniffer / Re: PCB design
@ladyada: hmmm, I can see your point. On the Eagle schematics it says: "this work is licensed under the Creative Commons NONCOMERCIAL License" - yes there is a typo!
/EDIT
Eventhough noncommercial is certainly a restriction (and would apply to anyone producing and selling the design) making it not completely open, I am not sure if Ian and Jack have come to a final decision under what kind of license they will release the design once it is completed.
/END EDIT
@Jack: nice to see the 16-bit transceiver instead of the 8-bit buffer ... makes it even more versatile now.
I prefer the numbering to start with '0' as this seems to be the most commonly used notation for data and address busses in data sheets and designs - at least I am more used to it and it will make referencing easier when using the SUMP client.
355
Bus Pirate Support / Re: Unbricking a WRT320N with Bus Pirate?
- WRT160N V3 (S/N#: CSE41J...)
- WRT160NL V1 (S/N#:CUR01J...)
- WRT320N V1 (S/N#: CUH01J...)
- WRT610N V1 (S/N#: CTG01J...)
I started with the WRT160Nv3 but couldn't find any external "hidden" serial ports inside the Internet/Ethernet connectors nor could I find a serial port header on the PCB
There is only one 12-pin header (JTAG, maybe combined JTAG/serial port) - doesn't look very promising, yet.
Moved on to the WRT160NLv1, didn't open it yet but found this:
... external antennas, an Atheros 9130 CPU and it's supposed to have a JTAG header (2x7 pin 0.050mil) ... interesting.
Then I took a quick look at the WRT320N. When looking at the picture I had taken of the "hidden" serial port inside the WAN/Internet connector I saw contacts inside the Ethernet 3 connector. Not sure what they are, they are not labled ..
... 
Next I will hook the Bus Pirate up to the serial ports on the WRT160NL and WRT320N ...
356
Bus Pirate Support / Re: Bus Pirate v3 plastic case
357
Open Bench Logic Sniffer / Re: Parts list (rough design, options)
I suggest to add pads/vias for a .100 spaced 2 pin header on the serial interface (TX, RX) between the PIC and the FPGA. This would allow
a) to monitor the interface between the PIC and the FPGA (i.e. with two Bus Pirates or more sophisticated line analyzers) during development and for debugging should anyone chose to develop different designs/enhancements for the FPGA. GND is available from the legacy UART connector. In production the header would not be populated and it will be up to the user to add the header ...
b) connect the FPGA directly to a PC (using a USB/RS232 converter cable) or some other MCU/interface instead of the PIC (so it may require a "ignore FPGA" mode for the PIC).
By now I have a SUMP LA implementation running on the Pollin CPLD board and I experienced sporadic communication problems at 9600 Baud. First I wasn't sure what caused the problems but by putting a Saleae Logic LA on the serial output of the FPGA I was able to establish that the problem was caused by a bad oscillator (runing almost 5% slower than specified ... well outside the tolerance). Now I have the Saleae hanging on the serial interface of the CPLD all the time and can check the communication between the PC and the CPLD whenever I want. So I have a JTAG interface connected as well, I prefer to use the line monitor whenever I experience communication problems.
(while writing this, Jack posted the latest PCB update ... looks better every day
To my surprise I found a 2 pin header between the FPGA and the PIC, first I thought he was able to read my mind until I realized it is the header for Ext_Trigger_In and Ext_Clock_In ... taking up the place I thought the "monitor" header could have fit in ... now it will become more difficult to fit this header on the board).
Now for the buffer/transceiver/resistor (probe header) discussion:
I am inclined to agree with RichF and Jack - sounds like a contradiction? Not necessarily ...
Right after entering this discussion, I accepted that this is Ian's and Jack's project. Since someone has decided "to beat a dead horse" it won't make much difference if the dead horse gets beaten even more ... so here we go
1. 22 Ohm resistors for serial terminators sound ok from my experience, too (39 Ohm did well in some other design) but experience isn't everything. I am against terminators on the "primary" header. Jack's arguments - in particular the following - can't be dismissed:
- it will make the design (even) less DIY, require a larger PCB and kick manufacturing cost up
- if people want to use R or RLC terminated high-end probes the resistors will mess with the impedance
- the goal is 50MHz and I don't expect the need for termination to suppress crosstalk at up to 50MHz
- if anyone wants to terminate the lines he/she can go for the other 16 channels on the unbuffered Wing header - the plan is to develop a buffered/terminated 16 addon Wing anyway - use RLC probes or add a small board with terminators/filters to the "primary" header (not sure if that will help much and not add more problems, so).
2. For the 8 vs 16 buffered lines on the "primary" header and the question of using buffers or transceivers:
- It looks like there is space for 16 buffered but not terminated lines - take RichF's idea and make it a 1x18 (maybe 1x20 - 2x GND, +5V, +3.3V) header instead of a 2x9 header - routing should not be too difficult if following RichFs general concept, keep the resistors out ... there would be no need to route traces to the edge side of the header ...
- make the "primary" header 16 buffered (input only) lines - most people will use the device as a LA (and isn't that primarily what this project is about anyway?) only and may never use the wing header but they would love to have more than 8 channels for sure ... those who want 32 channels will have to use the wing header as well (32-bit will work only up to 100MHz anyway)
- at above 100MHz the VHDL design is 16-bit only and will serve the Wing header only - allowing for the use of customized Wing boards - that's the place to put bidirectional lines/transceivers, level shifters, filters, terminators ....
In short: "primary" header (Port A) 16 buffered (input only) non-terminated lines.
Updated the block diagram according to the latest schematics (almost
:
358
Bus Pirate Support / Re: Unbricking a WRT320N with Bus Pirate?
It is said that Cisco/Linksys has special cable adapters to connect to the "hidden" serial port inside the WAN/Internet connector of those routers. They are special made and only used in engineering, production/quality assurance. I take a close look at the connector once I have the routers on my table.
Probably the first thing I will do before tearing them open is trying to connect a Bus Pirate to this hidden serial connector. Will let you know ...
Since everything that can't run away must be hacked and modded I will look into replacing the internal antennas with some externals ... the warranty will be void after opening the housing anyway ...
359
Bus Pirate Support / Re: UART live capture and blocking input
Thnx
360
Bus Pirate Support / Re: Unbricking a WRT320N with Bus Pirate?
The UART table/connection diagram was drawn by me earlier today.
You have my permission to use any of my pictures, drawings, posts and comments on this board on your websites and anywhere else you like. Consider them to be licensed under GFDL - GNU Free Documentation License (I prefer this license as it includes the "don't send the lawyers my way" clause(s)).
The same applies to pictures, drawings, diagrams (including schematics and PCB layouts) I send you via email or make them available to you via file sharing service (by sending you links) unless I state explicitly that other regulations and/or restrictions shall apply or in case they contain copyrights or license notes by others then those shall apply.
Once I will receive the routers I will tear them open and take pictures and write up a short report on how the Bus Pirate can be put to use on them. Since the source of the firmware has been published by now and I have a working MIPS toolchain I may attempt to take a pick at the JTAG interface with the Bus Pirate as well
... oh, good old memories Uwe