This is a port of Brian Bennett's NES fpga emulation modified for Pipistrello LX45 by Magnus Karlsson. At boot-up the SD-card is checked for a game file (game.nes). If found it will load and start the game, else it will default to Super Mario Bros. which is pre-loaded in BRAM.
Hookup: Video-out via HDMI connector (VGA resolution) Sound-out via audio connector Support for up to 2 NES game controllers connected to the top row of the PMOD connector. PMOD connector hookup (top row, from right to left): CLOCK, LATCH, DATA OUT(1), DATA OUT(2), GND, POWER
A new version of the Open Bench Logic Sniffer code is now available for Pipstrello-LX45. This version has the capture buffer increased to 64 MB by using the onboard LPDRAM instead of using internal BRAM. The capture rate is still the same, i.e. it still support 200 MHz 8 and 16-bit capture as well as 100 MHz 32-bit capture. The serial communication speed is set to 921600 baud.
The original SUMP protocol unfortunately has a capture size limitation (in hardware) to a maximum of 256k samples (512k samples in mux mode). This version of the verilog code has an alternative set of capture size registers that will allow up to 256M samples. However, the SUMP client on the PC must be modified to take advantage of the new registers so I have modifiled JaWi's OLS client to allow longer captures. BTW, it will also work with the current release of the SUMP client but with the capture size limitation mentioned above.
FYI, I have ported the Demon 3.07 code to Pipistrello LX45 FPGA board with the following changes:
1) The sample buffer size is increased by a factor of 8 from 24kB to 192kB 2) The interface is changed to serial (Pipistrello uses a FTDI 2232H High-speed USB chip) 3) The baud rate is increased from 115200 to 921600 to reduce the data upload time 4) The meta data has changed to indicated Pipistello implementation
I believe this is the largest buffer size of any of the "SUMP" implementations. It runs great with the latest JaWi OLS Java client.
The implementation uses about 22% of the slices and 96 block rams (out of 116 total). BTW, removing the advanced triggers reduce the size to about 7% of the slices making it quite possible to have this as an internal logic analyzer in a FPGA project.
More info and links to the complete XISE project and the bit file can be found at the saanlima forums (sight, the link got blocked, I guess you just have to google "pipistrello fpga").
