Yes, you need to update the bit file to the one with edge trigger support. The code for the PIC processor do not need to change.
One thing about edge triggers - while it's possible to specify several bits as edge trigger instead of level trigger, it only makes sense to set ONE bit as edge trigger, else it would need to see several signals having an edge exactly at the same time which might be unlikely to happen, especially if the sampling rate is high (like 100 MHz). An edge means that the corresponding bit in the sample has changed between two samples, if several bits are set to edge trigger then all have to change between the two samples.
I did send you a reply but maybe you did not see it. The version you use was based on a snapshot taken from JaWi's code repositiory (and given the name ols-0.9.8.SNAPSHOT at the time) but it was taken before the ols-0.9.7 SP2 release so it has the same lock-up problem as ols-0.9.7. You should try http://www.saanlima.com/download/ols-0. ... trello.zip instead, it's based on ols-0.9.7 SP2
Make sure the test mode check box is not set in the Capture->Acquisition popup menu. In test mode the unbuffered pins are driven by a test pattern which can be feed back to the buffered inputs to verify the functionality of the board.
I don't know much about the original SUMP vhdl implementation but I can give you information about the verilog version.
The code conversion from the original SUMP vhdl code to verilog that dogsbody did for Open Bench Logic Sniffer really only supports the SPI interface used on OBLS. The code does include some serial code but it's broken (wont compile) and even after it's fixed up so it compiles it doesn't work. When I ported to code to Pipistrello I rewrote the serial code from scratch and it seems to work great.
Here is a pointer to the Pipistrello verilog code using BRAM memory that I think can be used as a starting point for you. It uses 192 kb of BRAM so you might have to change that. It also uses 921600 baud for communication but this is easy to change using defines. http://http://www.saanlima.com/download/pipistrello-v2.0/Pipistrello_OLS_192K_3.07.zip
AFAIK, nobody has implemented support for advanced triggers in a SUMP client. Since edge triggers are really useful I decided to add it to the basic trigger mode in the verilog code as well as implement support for it in JaWi's SUMP client. Here is a screen shot of the trigger setup menu with edge triggers. If the edge bit is set then the value bit means rising/falling edge, else it means high/low level. You can mix and match edge and level triggers.
See attached zip file with verilog source (bitfile in the XISE directory):
Pipistrello OLS is basically the OpenBench Logic Sniffer (OLS) code ported to Pipistrello. Everything works the same way as OLS but with 64 Mbytes of buffer vs 24 Kbytes in OLS. The code exists in two flavor: serial @ 921600 baud, and FTDI async FIFO.
The serial mode is there just for compatibility with JaWi's client (you can change the baud rate in his client) but not really useful for larger sample sizes - it takes about 9 min to receiver the full 64 Mbytes vs about 8 seconds in FTDI async FIFO mode.
One thing to note is that the SUMP protocol has a 256K sample limitation (the readcount and delaycount are 16-bit values crammed in a 32-bit register) but I extended the protocol with two new 32-bit registers for readcount and delaycount. This is done in a backwards compatible way (i.e. you can set the readcount and delaycount be either writing to the combined register or to the new individual registers, the last write wins).
As I see it, there are several options for supporting Pipistrello OLS in your code (from simple to hard): 1) Add a baud rate select option so that 921600 baud can be selected 2) 1 + add the option to select up to 256K samples (maybe based on reading the metadata) 3) 1 + support for the new extended readcount and delaycount registers + the option to select up to 64M samples 4) 3 + add FTDI async FIFO interface option
I think it would be great to have support for a high performance OLS in your code and I'm willing to help you if need be.
This is a port of Brian Bennett's NES fpga emulation modified for Pipistrello LX45 by Magnus Karlsson. At boot-up the SD-card is checked for a game file (game.nes). If found it will load and start the game, else it will default to Super Mario Bros. which is pre-loaded in BRAM.
Hookup: Video-out via HDMI connector (VGA resolution) Sound-out via audio connector Support for up to 2 NES game controllers connected to the top row of the PMOD connector. PMOD connector hookup (top row, from right to left): CLOCK, LATCH, DATA OUT(1), DATA OUT(2), GND, POWER
The first version of Pipistrello (v1) did have synchronous FIFO mode support for applications like this and I have ported the verilog code over to use that instead of serial communication. I wrote a quick test (just a small C program linked with ftd2xx) that would setup a 64 MB capture and then receive the data, and got over 29 MB/s transfer speed.
The version of Pipistrello that's now available (v2) rearranged the FTDI ports to get JTAG on the A port so only async FIFO mode on port B is now available. Still, this should do about 9 MB/s so a full 64 MB capture would take about 7 seconds to download. I will change the code for async FIFO interface and verify this number.
BTW, I have been in contact with Jan Williem (the author of the JaWi OLS client) and he is very interested in adding FIFO support to the client.
A new version of the Open Bench Logic Sniffer code is now available for Pipstrello-LX45. This version has the capture buffer increased to 64 MB by using the onboard LPDRAM instead of using internal BRAM. The capture rate is still the same, i.e. it still support 200 MHz 8 and 16-bit capture as well as 100 MHz 32-bit capture. The serial communication speed is set to 921600 baud.
The original SUMP protocol unfortunately has a capture size limitation (in hardware) to a maximum of 256k samples (512k samples in mux mode). This version of the verilog code has an alternative set of capture size registers that will allow up to 256M samples. However, the SUMP client on the PC must be modified to take advantage of the new registers so I have modifiled JaWi's OLS client to allow longer captures. BTW, it will also work with the current release of the SUMP client but with the capture size limitation mentioned above.
FYI, I have ported the Demon 3.07 code to Pipistrello LX45 FPGA board with the following changes:
1) The sample buffer size is increased by a factor of 8 from 24kB to 192kB 2) The interface is changed to serial (Pipistrello uses a FTDI 2232H High-speed USB chip) 3) The baud rate is increased from 115200 to 921600 to reduce the data upload time 4) The meta data has changed to indicated Pipistello implementation
I believe this is the largest buffer size of any of the "SUMP" implementations. It runs great with the latest JaWi OLS Java client.
The implementation uses about 22% of the slices and 96 block rams (out of 116 total). BTW, removing the advanced triggers reduce the size to about 7% of the slices making it quite possible to have this as an internal logic analyzer in a FPGA project.
More info and links to the complete XISE project and the bit file can be found at the saanlima forums (sight, the link got blocked, I guess you just have to google "pipistrello fpga").
