31
Messages
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Messages - rasmus
32
Open Bench Logic Sniffer / Re: "Capture Aborted! Device Not Found!" after update
33
Open Bench Logic Sniffer / Re: (Near) realtime cq. continuous mode acquisition
By the way... RLE does not reduce peak data rates. It only reduces average data rates.
34
Open Bench Logic Sniffer / Re: Status of RLE
32-bit (31-channel) RLE works as before.
16-bit (15-channel) RLE works (I think) but the client doesn't support it yet. You'll see the raw RLE data in the client.
8-bit (7-channel) RLE works with the same caveats.
All RLE modes time out and go into normal sampling mode after 20 seconds if the memory isn't full by then.
Known bugs:
RLE does not work reliably with sample rates below 10 kHz because of how the timeout works.
The first run after changing either channel groups or sample rate does not yield reliable data.
35
Open Bench Logic Sniffer / Re: Status of RLE
36
Open Bench Logic Sniffer / Re: Status of RLE
37
Open Bench Logic Sniffer / Re: (Near) realtime cq. continuous mode acquisition
For example, the following 3-channel data...
000
111
000
000
000
111
In a 4-bit coding scheme would be encoded as...
0000
0111
0000
1010 <--- This sample represents two repetitions of 000
0111
Yeah I don't think CPU is an issue. It's mainly a RAM size-issue when dealing with long recordings.
38
Open Bench Logic Sniffer / Re: (Near) realtime cq. continuous mode acquisition
That said I don't see any reason why RLE wouldn't work, except that it would really only serve to transform the disk size problem into a RAM/CPU problem.
39
Client software / VHDL RLE updates not supported by client
15-channel and 7-channel RLE would work analogous to the 31-channel RLE that we have now.
31-channel RLE: (Already implemented in the client.)
Channels 0 to 30 are used for samples and run-lengths. Channel 31 is the RLE flag (=0 for a sample, =1 for a run-length).
This mode can encode runs of up to 2G samples, which is actually a problem, because signals with little change in them could take hours, days, weeks or years to fully record depending on the sample rate. I'm going to add a timer that stops the RLE recording after a certain number of seconds (the timer could be made user configurable).
15-channel RLE:
Channels 0 to 14 are used for samples and run-lengths. Channel 15 is the RLE flag (=0 for a sample, =1 for a run-length).
This mode is useful when you're sampling 15 or fewer channels and you have no runs significantly longer than 32k samples.
7-channel RLE:
Channels 0 to 6 are used for samples and run-lengths. Channel 7 is the RLE flag (=0 for a sample, =1 for a run-length).
This mode is useful when you're sampling 7 or fewer channels and you have no runs significantly longer than 127 samples.
Edit: Attached a test bitstream.
40
Client software / Re: Jawi's Logic Sniffer client software - support and bug reports
41
Open Bench Logic Sniffer / Re: Status of RLE
42
Open Bench Logic Sniffer / Re: Status of RLE
It certainly seems as if certain computers generate certain noise profiles on the USB cable.
43
Open Bench Logic Sniffer / Re: Status of RLE
I also tried it with my laptop with the power cord disconnected, running on batteries, since that can sometimes help with noise. No difference.
44
Open Bench Logic Sniffer / Re: Status of RLE
That's interesting. I ran the very same tests again and I still get the same results as before 100% success on the Inside, 50% success on the Outside and 0% on the Test mode. Always interesting when you get different results with the same design. Maybe your Spartan 3E is a better sample than mine is.
45
Open Bench Logic Sniffer / Re: Status of RLE
In this firmware, the 32 signal inputs to the FPGA are left unconnected (commented out in the ucf-file). The 'number scheme' (inside, outside, test mode) in the client software selects between three different internally generated test signals (essentially clocks of three different frequencies), each attempting to provoke errors in the RLE module in the FPGA. I've only made changes to the ucf-file and one of the processes in the Logic_Sniffer.vhd file. Everything else is exactly as in firmware version 2.12. The project is too big to be attached to this message, but I'll attach the two source files that I've made changes to in case anyone else wants to do further testing.
The inside signal is a 6.10 kHz clock.
The outside signal is a 3.05 kHz clock.
The test mode signal is a 1.53 kHz clock.
If anyone would like to upload the firmware to their OLS and run each of the number schemes (inside, outside, test mode) with RLE and test for the success rate of each signal, that might be useful. My OLS has roughly 100% success rate with the inside signal, 50% with the outside and 0% with the test mode, but maybe yours is different.