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Messages - rasmus

2
Open Bench Logic Sniffer / Re: Re: Status of RLE
Oh, I believe the off by one is there by design. I didn't design it that way. I believe Jonas, the author of the current RLE module, designed the coding scheme and I was also confused by the off by one feature when I simulated his RLE module, but the scheme makes sense when you think about it. The count represents repetitions of the one previous sample (not the total run length of the run as you might expect).

I'm not able to recreate the problem with 100 MHz sample rate in the 0.9.2 client.
3
Open Bench Logic Sniffer / Re: Status of RLE
0.0.7

The finish command is now 0x05.
Timer removed in favor of the finish command.
The code has been optimized and made easier to read.
6
Open Bench Logic Sniffer / Re: Status of RLE
Right, that's better.

Anyway, with regards to jgover's idea to use a software timer instead of a hardware timer: that would certainly reduce resource use in the FPGA significantly. We're talking 5% to 25% depending on which resource you're looking at.
7
Open Bench Logic Sniffer / Re: Status of RLE
Aha, I see... Well, it should be a short command. The finish command is meant to be used by a pushbutton in the client and potentially by a timer in the client. It could also be useful for people who want to script a series of captures.
8
Open Bench Logic Sniffer / Re: Status of RLE
It's a very good idea to use a dedicated RLE flag signal, especially if that means we can use the full 32, 16 and 8 bits for channel capture and run-length counts, but I think you will always need to know the memory configuration in order to know when the counter hits it's maximum number.

32-bit mode would use a 32-bit counter, 16-bit mode a 16-bit counter and 8-bit mode an 8-bit counter.

jgover's scheme is equivalent to a timer, but the most flexible and responsive solution is to send a command from the client to finish the RLE capture. The hardware timer wouldn't really be needed anymore.

Edit: Like I said before it's not obvious that the scheme jgover proposed would use fewer resources on the Spartan 3E. The only way to find out is to test it and compare the results.
11
Open Bench Logic Sniffer / Re: Status of RLE
Do you mean that the current PIC firmware passes on the 04 command on the SPI bus, or is that something you need to add?

I do get the expected response to 02 when I send it to the OLS, so something is working.
13
Open Bench Logic Sniffer / Re: Status of RLE
ian: Sure, metadata should be simple enough, but only if there is a PIC firmware that supports those commands. Otherwise there's no easy way of testing them.

jawi: The hardware timer starts ticking when it gets a '1' on the run signal, which I suspect is the final trigger event.
15
Open Bench Logic Sniffer / Re: Status of RLE
It's not clear that way would use less resources in the FPGA than the timer way. The RLE module is free software, so you're free to take a stab at it and see if you can slim it down.

The finish now feature is probably something that the user wants. Responsiveness is good. You might think you want a 60 second timeout, but then you realize the data you need has probably already been captured. Finish now!

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