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Messages - ian

1
General discussion / Re: Forum messages
I'm going to flush all the PMs. There was some bug in the transfer, and I've seen a few people have issues now.
3
Bus Pirate Development / Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
X

For the bigger display - SPI interface pins are listed in the pin description, but there are no IM0...3 pins to select the mode (maybe this chip works differently). The schematic also doesn't mention an SPI mode. I have not looked at the ILI9806E datasheet, maybe the mode is selected differently than the smaller version.
4
Bus Pirate Development / Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Currently I'm using KD028QVFMA017, for capacitive touch we're using KD028QVFMA017-C002A.

Startek's website is down, but when it comes back up the 4.3" datasheet is here and I'll have a look.

In general driving all those 16bit pixels from SPI seems slow. We have room for improvement using DMA to transfer the background images from the flash chip to the display, but i have this nagging feeling that we'll need to use an 8 or 16bit parallel interface  when we get to a future v2 or v3.
7
Bus Pirate Development / Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
X
It's been a bit quiet here, but we've nearly completed debugging of v1d. v1e is routed and we'll make a small batch of them (10?) soon, but probably after spring festival.

This is the prototype display board for v1e:
*2.8" IPS LCD with capacitive touch display. The capacitive touch sensor is I2C based, so we added an I2C bus and interrupt pin to the flex connector
*2 silicone buttons with RGB LEDs under each. The buttons are controlled through a TCA9534 I2C IO expander, basically a 5volt tolerant PCF8574 at half the price. The TCA9534 uses the same I2C bus as the capacitive touch sensor, and gets a dedicated interrupt signal on the flex connector
*6 additional IOs (routing in progress) from the unused pins of the TCA9534
*RGB LEDs (SK9822) share an SPI bus with the LCD. The SK9822 runs at 5volts and uses a two pin protocol that can be driven by an SPI peripheral, but it doesn't have a chip select pin so it can't share an SPI bus with other peripherals. We use a 74HCT573 as a level converter (3.3->5volts), and the 573's latch pin as a pseudo chip select
*The board is now powered from VUSB (5volts) and has a 3.3volt regulator

X

The schematic is nearly finalized:
*MISO on SPI should be jumpered. This leaves a disconnected pin between VUSB (5volts) and the 3.3volt logic pins
*Route unused IO pins to a header
*Run LCD backlight from VUSB
8
Bus Pirate Support / Re: Can Bus Pirate be used as an I2C comms tester?
Quote
I am not able to post a reply due to some technical issue, but in response to your reply:

Thanks for the swift reply Ian :-) I guess I'd really just be trying to ensure that behavior outside of the protocol does not put the device under test into an undesirable state and to prove that if followed by a correctly formatted command the device under test recovers and responds appropriately. for example:

* Configure the I2C tester to send a valid packet to DUT but configure the tester to put in a STOP after 4 bits of the address
* Write a byte to the DUT, but corrupt it with a STOP condition after each bit in turn i.e. START + STOP, then START + first bit + STOP, then START + first 2 bits + STOP, ... until START + first 7 bits + STOP then issue a valid command to ensure that I2C comms are still okay.
* Same as above but for a READ
* Send a start condition then the address followed by the stop condition (no data) Followed by a read of the DUT to check all is well.
* Plus maybe also play with clock stretching, different clock speeds and maybe even play with pull-up R values

Cheers
9
Bus Pirate Support / Re: Can Bus Pirate be used as an I2C comms tester?
That's a really nice idea. The current hardware doesn't do that and is probably ill suited to do it properly (at full bus rates). The next version has an FPGA and it can definitely be adopted to test all conditions.

Do you have a list of tests to perform? I'm going to start on the I2C HDL for the FPGA very shortly, I can see if I can add it.
10
Bus Pirate Development / Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
X

The HDL is complete enough to start testing on real hardware. This update puts almost every feature under control of the state machine in the FPGA so commands can be pipelined with repeatable precision. Commands (write/read SPI, set/clear pin, measure voltage, update PWM, enable pull-up resistors, etc) are pushed into a FIFO buffer using a 17bit command/data protocol inspired by the interface of ST7789-based LCDs. When the state machine is enabled the commands are processed in one continuous stream.

Verilog HDL for the FPGA is on github, the latest updates are currently on the command-data-refactor branch. A synthesized version of the bitstream is attached below.

@giggiu16 has already build his own v1d. I have a few more boards if you want one. PM me.
11
Bus Pirate Development / Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)
Are there any fault indicator bits that survive a crash/stack overflow? I thought maybe we could use that and a watch dog timer to reset into bootloader if anything goes wrong. The pic has a persistent bit that survives a reset in addition to the stack overflow bit. If there is something similar we can combine them to enter the bootloader without external pin.

however I agree an external pin is needed for worst case scenarios.
12
Bus Pirate Development / Re: Bus Pirate "Ultra" pipelined and non-pipelined operations
Code: [Select]
    `define CMD_DIO_WRITE 8'h00
    `define CMD_DIO_READ 8'h01
    `define CMD_DIO_TRIS 8'h02
These are commands to read/write and set direction of the IO pins. Send CMD_DIO_WRITE to FSMC address 1, then push as many pin changes (as the lower 8 bits of the word, so 0x00FF for all high, 0x0000 for all low) as you want to FSMC address 0. READ and TRIS word similarly.

Code: [Select]
    `define CMD_PERIPHERAL_WRITE 8'h03
    `define CMD_PERIPHERAL_READ 8'h04
Sends a word (16 bits) to the peripheral (SPI, I2C, etc). The purpose/function of each bit depends on the peripheral. For SPI the bottom 8 bits are the data to send. The top 5 bits are how many times to repeat, and bottom 3 bits are how many bits to transmit. One the command has been issued it is possible to continue reading or writing without sending another command, this improves our throughput where it matters most.

Code: [Select]
    `define CMD_DELAY 8'h05
Send this command followed by how many clock cycles to delay as a 16 bit word.

Code: [Select]
    `define CMD_PWM_ON_PERIOD 8'h06
    `define CMD_PWM_OFF_PERIOD 8'h07
Send command followed by 16bit on/off periods. write ON first, followed by OFF to correctly reset the PWM with the new period.

Code: [Select]
    `define CMD_ADC_READ 8'h08
Send command followed by a data word to measure voltage with the ADC. the lower four bits of the data word map directly to the 74HCT4067 select pins. Like all commands, send additional address data words to get another measurement on the same or different pins.

Code: [Select]
    `define CMD_LA_START 8'h09
    `define CMD_LA_STOP 8'h0A
Start and stop logic analyzer. No data.

Code: [Select]
    `define CMD_REGISTER_SET_POINTER 8'h0B
    `define CMD_REGISTER_WRITE 8'h0C
    `define CMD_REGISTER_READ 8'h0D
There is a 16 word configuration register that can be access through the command pipeline. CMD_REGISTER_SET_POINTER followed by a data word with register to access 0-15. CMD_REGISTER_WRITE enables writing at the current pointer. Send as many data words as needed, the pointer auto increments so that the configuration can be done in full with a single command followed by 16 words of data.

CMD_REGISTER_READ plus one data word with the number of registers to read (0-15). Reads starting from the register set by the register pointer command.

Code: [Select]
`define REG_BPIO_OE config_register[4'h0][BP_PINS-1:0] //pin output enable (1=true)

`define REG_BPIO_OD config_register[4'h1][BP_PINS-1:0] //pin open drain (1=true)

`define REG_HW_CONFIG config_register[4'h2] //misc hardware config (power supply? pullups? etc)
`define REG_HW_CONFIG_PULLUPS_EN config_register[4'h2][0] //set bit to enable pullups

`define REG_LA_CONFIG config_register[4'h3] //logic analyzer configuration. About to get a major overhaul
`define reg_la_io_quad config_register[4'h3][0]
`define reg_la_io_quad_direction config_register[4'h3][1]
`define reg_la_io_spi config_register[4'h3][2]
`define reg_la_clear_sample_counter config_register[4'h3][3]
`define reg_la_active config_register[4'h3][5]
`define reg_la_max_samples_reached config_register[4'h3][6]
`define reg_bpsm_reset config_register[4'h3][7]

`define reg_la_io_cs0 config_register[4'h3][8] //reserve upper bits for more SRAMs
`define reg_la_io_cs1 config_register[4'h3][9]

`define reg_la_sample_count rreg[4'h4] //unused currently, will be reworked

`define REG_ADC_CALIBRATE config_register[4'hA][0] //when set the ADC will run in calibration mode the next time the ADC_READ command is run

`define REG_PERIPHERAL_0 config_register[4'hC] //reserved for the peripheral configuration of each mode (SPI cpol, etc)
`define REG_PERIPHERAL_1 config_register[4'hD]
`define REG_PERIPHERAL_2 config_register[4'hE]
`define REG_PERIPHERAL_3 config_register[4'hF]

These are the 16 registers currently accessible from the CMD_REGISTER_x commands.

Code: [Select]
    `define CMD_SM_HALT 8'h0F
Halts the statemachine so the MCU can take over and perform operations. No data word needed. Needs to be reworked now that the registers cannot be accessed if the statemachine is halted :) Resume will be by pin or FSMC register write, not sure yet.

13
Bus Pirate Development / Re: Bus Pirate "Ultra" pipelined and non-pipelined operations
Code: [Select]
    `define CMD_DIO_WRITE 8'h00
    `define CMD_DIO_READ 8'h01
    `define CMD_DIO_TRIS 8'h02

    `define CMD_PERIPHERAL_WRITE 8'h03
    `define CMD_PERIPHERAL_READ 8'h04

    `define CMD_DELAY 8'h05

    `define CMD_PWM_ON_PERIOD 8'h06
    `define CMD_PWM_OFF_PERIOD 8'h07

    `define CMD_ADC_READ 8'h08

    `define CMD_LA_START 8'h09
    `define CMD_LA_STOP 8'h0A

    `define CMD_REGISTER_SET_POINTER 8'h0B
    `define CMD_REGISTER_WRITE 8'h0C
    `define CMD_REGISTER_READ 8'h0D

    `define CMD_SM_HALT 8'h0F
Here is the command set I've been working with. Write these commands to FSMC address 1, then pump the options/data into address 0.

Code: [Select]
`define REG_BPIO_OE config_register[4'h0][BP_PINS-1:0]

`define REG_BPIO_OD config_register[4'h1][BP_PINS-1:0]

`define REG_HW_CONFIG config_register[4'h2]
`define REG_HW_CONFIG_PULLUPS_EN config_register[4'h2][0]

`define REG_LA_CONFIG config_register[4'h3]
`define reg_la_io_quad config_register[4'h3][0]
`define reg_la_io_quad_direction config_register[4'h3][1]
`define reg_la_io_spi config_register[4'h3][2]
`define reg_la_clear_sample_counter config_register[4'h3][3]
`define reg_la_active config_register[4'h3][5]
`define reg_la_max_samples_reached config_register[4'h3][6]
`define reg_bpsm_reset config_register[4'h3][7]

`define reg_la_io_cs0 config_register[4'h3][8] //reserve upper bits for more SRAMs
`define reg_la_io_cs1 config_register[4'h3][9]

`define reg_la_sample_count rreg[4'h4]

`define REG_ADC_CALIBRATE config_register[4'hA][0]

`define REG_PERIPHERAL_0 config_register[4'hC]
`define REG_PERIPHERAL_1 config_register[4'hD]
`define REG_PERIPHERAL_2 config_register[4'hE]
`define REG_PERIPHERAL_3 config_register[4'hF]

CMD_REGISTER_x sets a pointer and reads and writes from this set of registers that control internal functions.
14
Bus Pirate Development / Re: Bus Pirate "Ultra" pipelined and non-pipelined operations
I'm in the process of refactoring the HDL to facilitate making everything possible into a pipelined command.

Currently I'm modeling the interface after the common 3/4/8bit/16bit RGB LCD interface. An 8 bit command is entered when a command/data pin is high. This is followed by 0 or more bytes of parameters/data. This should give the best possible speed for pushing and pulling long chunks of data from connected devices (eg flash rom).

Part of this change is to expand the 16bit FIFOs to 17bits wide. The extra bit tells the Bus Pirate statemachine if the word sets a new state or if it is data for the existing state. These FIFOs sit at register 0.

What I'm still not sure about is how to process "now" commands that need to be executed immediately and don't go into the FIFO. It could be a statemachine at the front of the FIFO that intercepts "now" commands (say 1xxx xxxx are immediately processed, 0xxx xxxx are put into the fifo). A second statemachine or a few control registers/status could sit at higher address. We'll see what's actually needed after the refactoring is complete.

One of the nice things about this setup, if it works, is we can eliminate a bunch of the static memory controller address lines and free up some FPGA pins while simplifying the PCB.

I'll document the command data interface here.
15
Bus Pirate Development / Re: Bus Pirate "Ultra" pipelined and non-pipelined operations
These commands are currently pipelined:
*Delays (ms, us)
*Bus reads
*Bus writes
*Pin read/write/direction
*ADC reads (on any pin, Vout)
*Pull-up resistors toggle
*Logic analyzer start and stop

These commands will be pipelined shortly via logic updates:
*PWM
*Frequency measurement

These commands will be pipelined in v1e and later:
*Power supply enable
*Power supply margining (DAC)