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Messages - brett
LiFePO4 is certainly not the same chemistry as Li-Ion or LiPo. The giveaway is the cell voltage, nominally 3v2 not 3v7. The charge and discharge thresholds are very different as @blarson notes. But then again, most 18650 cells you buy are Li-Ion not LiFePO4, so unless you have a certain supplier I'd go back to checking what your actual chemistry is.
http://ev-power.com.au/webstore/index.p ... -cell.html is an example cell that is LiFePO4.
As for current limiting and isolation, I would think that current limiting is still relevant, you want to protect against a device that has failed. And I think the isolation should be to isolate the battery from the load, and not the boosted, regulated output.
All things considered I should have also given it more time, I only allowed 4 mins like the printed instructions that came with the board said, even though on my first board I left it for closer to 10 (like it says on the web)
Found I had some 75mm wide stock single sided PCB so instead of buying a new larger board and cutting to 80mm, you guessed it, revised the board and shrunk 5mm off the narrow side.
Now I'm calling DONE for good. :)
Just to document the thought pattern a little more, here's a marked up version of the last image, red numbered boxes around the major component locations:
1 is the DS18B20 one-wire device plus a 2.54mm pin headers for extension off the board if needed. Data pin can go to pretty much any IO pin location.
2 is the 24LC256 I2C eeprom. The I2C pins must go to the identified pins.
3 is the WIZ812 module (40 IO pins in 2x10 x2 configuration). Only a small number of the pins are used in the SPI configuration I'm using. Some of the pins need to go to the SPI specific pins, then there are a number that go to the GPIOs. (Just above it is the 4pin header that will go to the RS232 daughterboard.)
4 is the Fez Panda IO header locations. These come directly from GHI's design files, are not separate-able at all, can only be moved as a block. One of the first things I did was take GHI's component-level design and strip out all the irrelevant components just leaving the headers so that I had precise header location rather than measuring them. The headers remain as individual items in the Eagle file - I couldnâ€™t really figure how to take a schematic plus board layout and make that a â€œcomponentâ€ so I just left it as-is and was careful not to move it.
5 is the SD card holder I talked about earlier and created a footprint for. Pin selection is fixed for the majority of the pins, except the outermost two lines on each side (the signal lines for the detection of card inserted and write-protect). As you can see the connections there were quite challenging. Because Iâ€™m making a single-sided board the routing was much a harder than it would have been had I been able to mount the card holder on the other surface (most lines unravel themselves). Oh well :)
I fail the ERC since there are unconnected GND and VCC nets (theyâ€™re connected by the Panda that I will plug into this board). I fail DRC (based on what I think I should use for home-built PCBs) on numerous things, the simplest is that I have a couple of manual wires that I have planned to cross, some of the harder ones are the clearance of header pads from the GHI files. I couldnâ€™t figure out how to deal with the crossed-wires without resorting to a new layer, but because I know what they are and that theyâ€™re irrelevant, I am fine leaving things â€œdanglingâ€.
Anyway, so besides all the issues I know about, the board really isnâ€™t something I can be bothered optimising beyond this â€“ I am sure thereâ€™s a lot of things I could do but again as a one off thereâ€™s no return on it, I am just moving on!
Thanks Ian for the 2nd visit :)
When I was deciding on the routing for ethernet and SD card detection pins (ie any that didn't have pre-defined destinations on the board), the best thing I found was figuring out the directions traces would run and deliberately chosing pins that gave the longest parallel runs. Once I did that, the layout seemed to go together really well.
To do this I didn't follow what a "traditional" layout process would be. I initially had added all the components in schematic view, and wired up the known / mandatory pin connections (like the SD card pins, plus GND/VCC). Then I went into PCB view and laid out what I thought would give me room for routing the other data lines. After that, I had a rest for a couple of weeks away from Eagle (this step is highly recommended but totally optional). Then I figured out what traces would come from where, and laid them out in my head as parallel runs - then figured out what pins I needed to connect to (and were available) and switched back into schematic view and connected the nets, then back on the PCB I laid out the traces.
(there, +1 for documenting things I learnt)
you're right, it is a little hard to make true detailed suggestions without schematics etc. But given the very specific nature of this project, plus the very limited "design" pieces (I basically am throwing down known devices and connecting them), I suspect there's not really much value to be had for either you or I in getting the files to look at them.
The main reasons I started the project log were:
* show off my first Eagle efforts (and how ham-fisted they were), and document some of my learnings along the way (although I didn't detail some of that shame on me)
* discuss home-etched PCBs incl what I thought would be the hardest part, drilling thru-holes - maybe get some tips from others who do prototype PCBs at home on limited equipment.
It wasn't really to get routing assistance, or electronics guidance, but to make some mistakes and learn from them.
I'd be interested to hear what your thought was about getting the files, what you'd look at and comment on etc, while I figure out a place to put them. In the meantime the next best thing I can do is a screenshot of Eagle in board view.