Thanks again EasyRider. I suspected it was busted. Just to clarify I have not enabled RLE and I've ruled out my cable too.
I'm going to try to get it replaced. Unfortunately, it seems there's no real support for this device either from SeeedStudio or from Dangerous Prototypes. I should have just paid a little more and bought from Sparkfun. They surely would have just replaced it for me.
[quote author="EasyRider"]This sounds kinda like your last channels are capacitively coupled instead of galvanically - ie. as if those traces were interrupted and not directly reaching the FPGA or the buffer. I'd inspect the relevant pins on both ICs closely with a magnifier looking for poorly soldered pins, possibly reheating the joints if a hot air station is at hand.[/quote]
Thanks for the ideas EasyRider. I actually looked at the FPGA solder joints with a magnifier but didn't see anything obviously wrong. I do not have a hot air station... I've heard of people using ovens are frying pans for this sort of thing...
Honestly, I bought this for debugging circuits and am not sure I want to try to fix it. I've contacted SeeedStudio (where I bought it), but they pointed me back to dangerous prototypes for support. I filled out there contact form, but haven't heard anything back.
I'd like to get this thing replaced... I would consider trying to fix it if I was able to get it replaced if it didn't fix it.
I just got my Open Bench Logic Sniffer yesterday, but there is a strange issue with channels 13-15.
If I connect anyone of those three channels to logic 0, it does not appear low in the capture (there's noise like it's floating or something). If I connect two of those three channels to logic 0, then I see all three as logic 0 even with the third disconnected. I've also done this with a clock and see the same behavior (one channel connected to the clock doesn't capture the clock, when I connect two then all three show the clock signal).
The other channels seem to work perfectly (I've only been using 0-15). I just updated the firmware and ROM to v1.01 and 3.07 and the behavior is still there.
I'm new to logic analyzers, so I could totally be doing something wrong, but I can't think what it is. I thought this behavior might be because of disconnected channels, so I connected them all to ground except the one I'm testing and see the same behavior.
I've also tested with Sigrok and noted the same behavior (but the software crashes for probably unrelated reasons - seems buggy ATM). I've been using the LogicSniffer "offical" client, otherwise.
