1
Open Bench Logic Sniffer / I2C monitoring capability...
with as much as 100mS delay between packets, at 400KHz. The sequence lasts for as much as
2 to 3 seconds. Is this possible with the logic sniffer?
So far the best I have been able to accomplish is the capture of 1 packet at which point the LS stops
capturing and dumps the data to the PC.
Any help would be greatly appreciated.