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Messages - danmoto

2
Open Bench Logic Sniffer / Dynamic capture for the OLS
Hi, based on my quick reading on the OLS, once OLS is trigger, it captures every clock cycle.  I am not exactly a FPGA guru by anymeans, but is it possible to capture on a change instead of every cycle?

The idea is this:  If we add a 32bit memory array for a counter, and a comparator for the input and last input state, we can extend the recording time significantly.  We capture only when we detect a change by the comparator, or a overflow of the counter.

The worst case where signal changes every cycle, we cut our memory in half for 32bit and 1/5 for 8bit capture.  But in the best case, we effectively multiply the memory by up to ((2^32)-1)/2 for 32bit and ((2^32)-1)/5 for 8bit.

Most likely this implementation will reduce the maximum bandwidth.  But I think it would be very useful for applications that require very long captures with bursty signals that have many gaps and delays.

Is this possible?

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