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Open Bench Logic Sniffer / Re: Tech questions from a potential buyer
You might like to read this thread, "Ground for External Clock"
viewtopic.php?f=23&t=5508
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Messages - tggzzz
You might like to read this thread, "Ground for External Clock"
viewtopic.php?f=23&t=5508
2
Open Bench Logic Sniffer / Re: Ground for External Clock
Quote
do one thing well, not two things badly
Hence I'd concentrate on ensuring the board functions without "suboptimal" surprises.
Thus:
- do add the extra grounded header pins to allow shielded probe wires
- don't bother with 100K pulldowns. If floating pins are confusing the LA they will be confusing the UUT. If not then the LA isn't being used effectively (e.g. should be using the external clock to ignore pins when the value is irrelevant)
- don't add the DAC. Programmable thresholds can be added externally -- and I'll be doing something similar for my requirements anyway!
- don't add a larger FPGA and external memory: that's a different product
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Open Bench Logic Sniffer / Re: Ground for External Clock
I would probably ignore the connector and simply solder a twisted pair directly to the connector and capacitor as you describe.
I would also verify that the clock receiver was simply a single high impedance input connected pretty directly to the connector. Then if the twisted pair is approx 100ohms, I would have a have a 100ohm series resistor at the clock source. A half-height signal would propagate down the twisted pair and be 100% reflected at the receiver; the receiver at the end would only see a clean full-height transition.
Strikes me that when the board is revved it would be sensible to add two ground pins to the connector, one for the clock and one for the trigger.
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Open Bench Logic Sniffer / Re: Ground for External Clock
The twisted-pair technique would probably be sufficient if and only if the twisted pair was "continued through" the clock connector JP9 to the ground plane. It might conceivably be sufficient to have the tp's ground going somewhere else and then have the signal wire glued to the board until it reaches the connector. I'd be prepared to try that if I had a 1GHz scope to see what the signal looked like -- but since that's what I'm thinking of making, I have a problem :)
Not having a ground for the external clock makes me wonder whether anybody uses the external clock input. Even at low clock rates, if the edge rates are normal then I would expect to see problems.
Anyway, thanks, and if anybody else has used the external clock input I'd be interested to know their experiences.
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Open Bench Logic Sniffer / Ground for External Clock
As far as I can see from the schematic, the external clock input is only available on JP9. However, I can't see a nearby ground connection, so I'm concerned about the signal integrity of the external clock.
What's the recommended way of connecting an external 100/200MHz clock to the OBLS?
Thanks.