When reading the flash programming specification of the PIC32 micros, an idea crossed my mind.
The MIPS core that Michrochip choose for the PIC32 already had a JTAG interface implementation (EJTAG),
and the pins are available on the outside.
Instead of implementing a separate programmer/debugger for 2-wire ICSP, they added a 2-wire to 4-wire
converter in front of the JTAG.
The ICSP programmer has to talk to the chip over 2 wires in a special protocol that uses a special synchronous
time multiplex to transfer the state of the 4 JTAG signals over 2 wires.
The internal 2-wire to 4-wire converter converts this back to 4 signals and sends it to the JTAG interface.
So, my idea was to implement this 4-wire to 2-wire converter in the CPLD of the Bus Blaster.
This way, one could use the Bus Blaster to flash and debug PIC32 micros with OpenOCD via 2-wire ICSP,
the same way as you would do it with JTAG, without having to care about the different transport layer.
Would this be possible?
I don't know what the Xilinx CPLD is capable of.