While Jawi is working hard in his spare time to implement advanced triggers in his client, I wanted to discuss some of the technical details.
Given a boolean equation: A or (B and TIM1)
how can we map this to the trigger sums in the advanced trigger? This seems very similar to FPGA synthesis. Does anyone have any pointers for me on where to look for more information?
I want to try my hand at VHDL and create a full state machine for complex triggers. I wanted to document it here so I can (hopefully) get some feedback and maybe help some people.
First, the Goal: To create a full state machine with transitions controlled by internal triggers and external trigger while maintaining compatibility with the sump protocol and operation.
To start I will list the sump operation that I need to maintain. This is mainly from what I see in the code. If there are other constraints, please let me know. I am not changing how the triggers detect conditions, just what they do when found. Thus I will not describe serial vs complex and demux and such. These will stay the same.
Internal Triggers (4) Trigger can either immediately start capture or upgrade trigger level by 1 Trigger can optionally delay for a certain number of clock cycles After delay, trigger either starts capture or upgrades trigger level by 1 There is no check of continuing trigger condition Triggers are not retriggerable trigger is "armed" one cycle after ARM goes high trigger goes to off state after signaling and stays off until ARM goes high Trigger signals 1 cycle after trigger condition Trigger only signals if trigger level is equal to or greater than configured level
Defaults: 0 delay Match (upgrade level) not start trigger on level 0 and higher
External Trigger Immediately initiates run
Trigger State 4 trigger levels (0 - 3) level 0 on arm level goes up by 1 on match from internal triggers level rolls over after 3
1 run level.
Sump protocol set trigger config delay trigger level channel for serial (Not needed) serial flag (not needed) start flag
So I want my design to maintain the above behavior, especially the configuration commands.
I was looking through the VHDL and came across the demux flag. I couldn't find much in the docs or a way of setting it in the interface. Can someone give me some hints?
I have a signal that goes high and low quite a bit. I am looking for a way to trigger if this signal stays high for a length of time, say 1 ms.
I see there is a delay setting in complex triggers and the protocol docs say "delay: If a match occures, the action of the stage is delayed by the given number of samples"
But i am still confused how to use it for what I want. Any ideas?
I just discovered this project and I am very excited about an open source analyzer. However, seeed (and their distributers) seems to be out of stock. Where else can I get one of these? Are there different revisions? What is the current revision?
I also noticed there is a logic analyzer project (lax) at gadget factory that runs on the papillo one (butterfly one) boards. How different is this from the OLS codebase?
