I think I posted this in the wrong place originally. Sorry for the dp.
Just got my first BP and by all indications it is working great. One of the first things I did with it was monitor the I2C bus on a project I have been working on. Basically several different PIC based boards communicating with each other. And I see an anomaly with the I2C data sniffed and captured by the BP. I am hoping someone can help me understand what is happening or how to fix it.
The new BP is v3b, firmware 5.10 (r559). From Seeed not Sparkfun
The PICs basically send a short command and update frame (the master) and the slaves respond to the subsequent read with a similar status frame. The I2C data rate is 100kbps. 5v PIC architecture. 4.7k pullups. All of this is working, and has been for a long time. What I am trying to do is monitor and perform a long-term data capture for analysis.
This is a normal captured sequence. There are two slaves currently in the circuit.
The master first writes 5 bytes to addr 01 (0x02 in the above), then reads from the same address. Then continues with a write to addr 02 (0x04 in the above) and then reads from the same address.
This is abnormal and is what I get out of the BP in I2C sniffer mode about 40-50% of the time on average.
It's always the last byte (I think) of the first sequence that is not captured by the BP. The second, third and fourth sequence are always spot on. There is typically a delay of between 100ms and up to 400ms between the last sequence and the start of the next new four sequences. So the sequences basically run like ||||--------------------||||-------------------||||------------etc.
I also connected a decoding logic analyzer to the same setup to compare results. Sampling at 24mhz I get very clean I2C clock and signaling and perfect decoding of all the data sequences. On the decoding logic analyzer I don't ever see the apparent lost byte on the first sequence like the BP often shows.
I know this is a lot to absorb and a funky problem but I hope someone will be able to offer some insight or suggestions.
I can reproduce the issue at will and can provide additional data plus data from the logic analyzer if that will help at all.
Just got my first BP and by all indications it is working great. One of the first things I did with it was monitor the I2C bus on a project I have been working on. Basically several different PIC based boards communicating with each other. And I see an anomaly with the I2C data sniffed and captured by the BP. I am hoping someone can help me understand what is happening or how to fix it.
The new BP is v3b, firmware 5.10 (r559). From Seeed not Sparkfun
The PICs basically send a short command and update frame (the master) and the slaves respond to the subsequent read with a similar status frame. The I2C data rate is 100kbps. All of this is working, and has been for a long time. What I am trying to do is monitor and perform a long-term data capture for analysis.
This is a normal captured sequence. There are two slaves currently in the circuit.
The master first writes 5 bytes to addr 01 (0x02 in the above), then reads from the same address. Then continues with a write to addr 02 (0x04 in the above) and then reads from the same address.
This is abnormal and is what I get out of the BP in I2C sniffer mode about 40-50% of the time on average.
It's always the last byte (I think) of the first sequence that is not captured by the BP. The second, third and fourth sequence are always spot on. There is typically a delay of between 100ms and up to 400ms between the last sequence and the start of the next new four sequences. So the sequences basically run like ||||--------------------||||-------------------||||------------etc.
I also connected a decoding logic analyzer to the same setup to compare results. Sampling at 24mhz I get very clean I2C clock and signaling and perfect decoding of all the data sequences. On the decoding logic analyzer I don't ever see the apparent lost byte on the first sequence like the BP often shows.
I know this is a lot to absorb and a funky problem but I hope someone will be able to offer some insight or suggestions.
I can reproduce the issue at will and can provide additional data plus data from the logic analyzer if that will help at all.
