How accurate is the timing of the OLS? And slightly off-topic: how accurate is the timing produced by crystal oscillators in general? I just tried to measure the duty cycle of some PWM signal, and in a perfect world that duty cycle should be off by at most 0.1us. That PWM signal is generated by some other uC running at 20MHz. Measuring the duty period with the OLS at 100MHz shows a duty cycle of roughly 1497.5 us. This is just out of curiosity, I do not need such an accurate signal, so my question is somewhat academical at this point.
Would maybe a "channel mask" be a good idea? I.e. a bit-mask used inside the FPGA to mask out certain channels before applying RLE encoding and storing the stuff in the sample buffer? The probe input ports of the OLS are floating, so if I do not connect unused probes to ground (or VCC) then I will have random noise on those unconnected channels. Or is such a feature already implemented? This is not an issue without RLE, without RLE the client can post-process the data to his liking, but noise on unconnected probe-inputs makes RLE encoding more or less useless. And connecting six unused cables to ground pins just to get a clean RLE-encoded I2C signal with the remaining two channels is a little bit annoying (but works, of course).
So my question is: is this functionality already there?
What toolchain is needed to compile the VHDL-core form source? Would I need to purchase one of the (not so inexpensive) kits from Xilinx, or are there other ways? Sorry if this question already came up, but I did not find anything about it in the wiki and forums. Of course, the mere fact that I ask this question implies that I'm a VHDL greenhorn, but OTOH, it is just a programming language.
