I have a desire to analyze a CAN bus. I was looking at the demo software for the Intronix LogicPort. They have a CAN interpreter that they use connected to the CANL line. From what I have found that will give you about 2.5v on the idle bus and about 1.1v for a dominate bit. It looks like they use a logic threshold of 1.6v (which is adjustable on the LogicPort) in order to analyze the bus. I have looked at the datasheets for the buffer and FPGA and am having a hard time getting a feeling for how this work work.
Any idea if this would work with the OLS? Is there a threshold that I could get with just a voltage divider? Any input or ideas would be appreciated.
Quick question.. Is any information available for creating a plug-in for SUMP? I am interested in a CAN interpreter. Is anyone already working on this?
Just curious if anyone has any info on when Seeed might be getting the next batch out the door. When I ordered they were showing an inventory of -81 units.
I have built the demo with the said line commented out and have been serving pages for the last 4 1/2 hours. Which is much longer than I was ever able to do before without a reset. Nice work Markus!