I'm not saying there are issues, just that I wouldn't expect it to be very well behaved. I may well be wrong. Your measurements definitely trump my impressions. A useful test might be to feed it some fast edges and observe the signal at the FPGA pin. This should give a good idea of signal integrity and cross talk. Main interest in my opinion would be without the pod, since most of the users won't be using the pods, and they may compensate for some issues.
If there's no ground plane (I didn't check the layout), then you're correct about the trace capacitance, I had automatically assumed a PCB designed for ~200MHz to have a ground plane. The buffer is likely an important component unless you use the unbuffered 'wing' input.
[quote author="Qwlciguk"]I'm not sure what you mean by "not very well behaved" with respect to the OLS input impedance. [/quote] What I mean is that I don't expect the impedance to be very flat across the frequency spectrum, since it's just an unterminated input straight into the buffer, without any form of damping or termination. Maybe even some resonance in the pass band. The HP RC matching network might help, although I expect their front-end to be much better given their RF background. Agilent scope inputs also tend to be better in this regard than other manufacturers.
[quote author="Qwlciguk"] I too was a bit concerned when I discovered that the flying lead set included an RRC matching circuit in each lead. So, I did some quick sims last night to see what effect it might have. It was nothing dramatic at all. Assuming 1.0pf and 100 Meg for the input buffer capacitance/resistance and including the RRC matching circuit, I see only very minor effects. There was ~2db of attenuation at 1 GHz.[/quote] This is not something I'd trust a simulator on. I highly doubt the 1pF spec, the PCB trace alone is probably more than that. -2dB at 1GHz would be extremely impressive, since scope vendors on the market never (?) succeeded in making a useful 1 Mohm front-end beyond 500MHz, it's all 50 ohm above that.
But if it works for you I guess that's all you should care about.
I would not be too worried about unknown toxicity of substances like IPA and acetone, since they've been in use for a long time, it's not some new 'wonder material' like asbestos was at some point. For occasional use, I wouldn't worry. Still, proper ventilation is important. Note that in some circumstances wearing gloves around hazardous chemicals is recommended against, since gloves slip easier than bare hands. Use gloves if skin contact is likely.
I would not put solder into my mouth and avoid inhaling flux vapors as much as possible. Definitely take more precautions and ask a friendly chemist with interpretation of the MSDS for more dangerous or unknown chemicals.
Are these pods readily available on the used market? I know people buying old HP/Tek logic analyzers often have trouble finding correct pods, and sometimes pay more for the pods than for the analyzer.
I'm convinced that HP did an excellent job on the design of those pods, but I would be worried about the matching of the OLS input impedance (which is probably not very well-behaved) to the RC network. Weren't these designed to be used with the special woven cables?
Matching a popular pin-out sounds like a good idea, as long as it still works with cheap 0.025" connectors (i.e. no Mictor or other exotic stuff). If the OLS were to be changed to match this pin-out, it may also be a good time to add a proper input circuit with some attention paid to signal integrity and maybe even a pull-down somewhere ;).
I don't think JTAG for the AVR32 is the same protocol as JTAG for the 8-bit AVR. The only non-Atmel hardware that supports debugging non-ancient AVRs are the various Atmel JTAGICE Mk. II clones, as far as I know. It took quite a while for them to appear, so it's probably non-trivial. The debugging protocol is not documented, only programming. The <= 28-pin AVRs (in DIP) don't support JTAG, the only debugging interface is the one wire 'debugWire', which is not documented at all.
Programming would be feasible if someone went through the effort of implementing it (not that much incentive since ISP works just as well and is widely supported), debugging probably not. A quick Google search suggests some programming support for AVRs, although it may not be mature.
[quote author="miro"]Alm, one issue is the "derivating" and "integrating" effect caused by the capacities as described in my post. At low _frequencies_ everything seems to be nice, when increasing frequency, the XCx plays significant role and the "DC" part of the signal at comparator side moves - thus to set the threshold might be difficult. M[/quote] There is a fundamental frequency at 20MHz, but there are harmonics (mainly in the edges) of well beyond 100MHz, so I would expect both integration/low-pass (slower edge rate) and differentiation/high pass (distortion in flat parts) to show up. With a short period, only the low-pass effect will show up, since there are no low frequencies to block (nothing below 100MHz). But it depends on the knee frequency for the various 'filters'.
I'll try to run the tests at 100MHz, should be easy now that I have the setup and software. Let me know if you have any other feedback. Any other circuit that would help our understanding of this issue? Simulations are less work, so my aim is to get an idea how well the simulation results match the reality. My current circuit is not what I consider the best, just the simplest. I think it would be hard to build something like the last circuits you showed, since the tiny capacitances like 3pF are likely to be swamped by parasitics (probably even more so on a real PCB with the ground plane within a few mm). But it seems a good idea to try something we've also simulated.
[quote author="miro"]Great! It seems you run the test at 20MHz. Did you try @100MHZ? M.[/quote] You mean the period? What does that matter? It's the edge rate that's significant, and that's well above 100MHz. I adjusted the period so the ringing was clearly visible, it tends to get lost at shorter periods.
It's about the step response (transient response) in this case IMO, and you could even use a single edge (infinite period) for that. I believe they also tested step response in the Agilent flying leads probe manual. Once you know the effect on rise time, you should be able to get a good idea what it will do with a shorter period.
I can redo the tests at 100MHz (I believe the pulse generator goes to 250MHz), but I would like to know why you think this is significant.
I did some real tests in solder instead of in silico yesterday. Test setup was with through-hole components soldered to a piece of copperclad. I soldered a 100mil header to the PCB vertically (i.e. pin 1 touched the bottom layer, pin 2 the top layer), and soldered the resistors/caps directly to the pins and the ground plane. I connected the leads from the Saleae Logic (which are probably 20-30cm?) and the included EZ-hooks to the 100mil header. See schematic for the circuit. This was loosely based on your simulations, although your results looked much nicer ;). Inevitable parasitics are not included in the schematic. Of course this kind of construction is not entirely representative for a double-sided etched PCB with SMT components, and the OLS wires may be shorter (?), but at least it's real.
As signal source I used a PG502 pulse generator (rise time <= 1ns, output impedance = 50ohm), through a RG-58 cable to a 50ohm feed-through terminator (you expect the signal to be terminated if necessary in a DUT). I used a 500MHz scope (set to average over 16 acquisitions) with FET probes (1GHz bandwidth, 1Mohm // <= 1pF input impedance). I clipped one FET probe to the BNC connector (ch2) (this involved ~10cm wires), and the other (ch1) across the 1M/22k load resistor. I clipped the ground hook (pin 3 in schematic) to BNC ground, and pin 1, 2 or none to the center pin. I added some automated measurements, although I would be hesitant to trust rise time measurements with this kind of ringing.
The 22k/82ohm version does look better in my opinion, but not very much. Signal loading (change in ch2) doesn't seem to change much with load resistance, seems the wires are causing most of the loading (not much you can do about this, except shorter wires or adding resistance). Didn't attempt to correlate
I planned to try it with real digital signals (will have to see what kind of fast digital signals I can find, don't think I have any logic faster than HC), but ran out of time. May continue later if the results turn out to be useful.
[quote author="miro"]Alm, here is a recommended _big_boys_ LA circuit for a _flying wire_ to the _pod's_ input. Assumption: the pod's input impedance is 1k II 3+1pF. Maybe they need to move the stuff above the zero a little bit.M.[attachment=0][/quote] Which circuit did you base this on, one of the Tek probes you linked to? Are C3/R4 part of the DUT (output impedance) or a tip resistor? I assume the former since you use point B as reference. The parasitics sound optimistic, compared to the quoted 33nH/inch (which seems high to me). 1pF between two adjacent wires also sounds low, and 0.3pF on the PCB will require very careful construction (air wiring?).
Edit: probably based on that last Agilent appnote you posted, although I can't find a direct equivalent. Source termination/damping is a fine solution, but I don't see how that would work for the OLS (unless people are designing their boards with a custom OLS header).
Performance looks good, although the large amount of low-pass filtering probably helps. I think some degree is acceptable, since we're limited by sample rate anyway. I wonder how much increase in rise time is acceptable. A LA won't actually measure a rising edge, so as long as an edge is significantly faster than 5ns (min. sample interval), it should be fine. Rise times add as sqrt(sum(r(i)^2)) for Gaussian systems, so a small rise time doesn't add much to a larger rise time. Did you find any reference for a relation between sample rate and max. rise time for best fidelity? My guess would be something like 1ns for a 5ns sample interval (which would make a 1ns edge 1.4ns, a 3ns edge 3.2ns, and a 5ns edge 5.1ns).
[quote author="miro"]Also 1kohm input DC resistance is too low, people say.[/quote] The stuff Howard Johnson works with, like high-speed LVDS drivers, will probably have a fairly low output impedance. But most OLS users will probably be using much slower circuits, some even open drain. Atmel recommends at least 10k pull-up on the reset pin of an AVR for debugWire to work, so 20k may actually on the low side. 10k is also sometimes used for I[sup:]2[/sup:]C. Both are perfectly valid signals to probe with a LA IMO.
Our speeds are relatively low, max sample rate is 200MS/s, highest repetition frequency (!= bandwidth) we can measure is 100MHz, bandwidth 350MHz assuming my 1ns rise time number. Not exactly at the limits of high-impedance probing, Howard Johnson is talking about GHz signals, which present completely different issues (eg. capacitive loading becomes huge, you can almost ignore any large-value resistor it it's shunted by any capacitance). Transmission lines would make our lives much simpler, but don't seem feasible.
[quote author="jack.gassett"]So what is it that you want to accomplish with the comparator? If you are just looking to reduce the propagation delay then you might consider using a FET Bus Switch, they have near zero propagation delays and allow for bidirectional I/O.[/quote] Adjustable logic threshold?
Building a prototype wing sounds like a good idea if we decide to go ahead. If it turns out to be a good and affordable idea, the OLS layout can be changed to incorporate this.
I don't think external pods are a good idea. They make sense if you have a huge logic analyzer; the OLS is barely larger than a pod. Adding external pods also adds extra costs and complexity (more PCBs to manufacture, more things to find a case for). Just using shorter wires will accomplish almost the same. The only advantage of pods is that you can have multiple pods on multiple places in a large DUT.
[quote author="miro"]Alm, here is the 20k termination (I think it is good to have it there to define input DC better) and 82ohm tip resistor. Of course the tip resistor does low pass filtering (and thus it limits the max bandwith) so the signals are looking nicer. [/quote] But the yellow signal (B) also looks better, and that's down to reduced reflections IMO. Might be a good idea to also test without the 'cable'/LA attached, to see what the unloaded signals look like. That should be the benchmark. I would also be careful with completely relying on simulated results, since real world parasitics (eg. flying wires are not a transmission line, not even close) may very well dominate.
The tip resistor looks like a good idea, but has mechanical difficulties (how do you connect it to the wires / connectors / clips?). This is why scope probes (and possibly LA probes?) use NiCr wire in the coax.
[quote author="miro"]The 74f40 is used because it is the only fast logic I have in this simulator(:-(. Maybe the LTspice has better libraries..M[attachment=0][/quote] Will see if I have time to do some work, can't promise anything, though.
[quote author="miro"]Alm, to this agilent probe - they have there 20k in series, but the connector impedance there is 75ohm. Assuming it is 75ohm dc, this makes a divider (20k/75)- maybe they use some ~ghz mmic amplifiers for each channel at the LA input (and work with mV levels instead of cmos/ttl what is even better).M.[/quote]
Looks like you're right. Note that it's referenced to 0.75V (guess that's their minimum threshold voltage?).
[quote author="miro"]http://www.tek.com/products/accessories/logic-probe.html[/quote] Do any of them have sufficient documentation to be useful?
[quote author="miro"]Alm, the agilent flying wire probe is an interesting piece of hw. It is a differential probe (pos+gnd,neg+gnd), in addition you may use 82ohm tip resistor and 160ohm damping wire to match the dut.. The DC is 20kohm, but DC plays minor role in this game..see the probe's equivalent circuit there, nice.. M.[/quote] And this is just a simplified equivalent circuit as a model for circuit loading, the actual circuit is probably much more complex. But they are used with up to 8GHz logic analyzers.
Yes, DC is insignificant for something like a 50MHz clock signal, but the trouble with digital is that signals have an extremely large bandwidth. You may have those 1.1ns second edges from your example, these contain frequencies of well beyond 300MHz (although we don't really care about those harmonics in a 200MHz LA). But you also have constant signals that are basically DC (eg. MCU reset pin), or just slow signals (I[sup:]2[/sup:]C). For something like an SPI /CS line, you have fairly fast edges (same as the other lines), but often a low pulse rate (depending on how long it spends talking to the same IC). If the DC resistance were insignificant, Agilent would have made it lower, since that makes life easier.
Thanks for the simulations, the series resistor appears to be more important than the termination. Is there any disadvantage to the series resistance apart from a 0.05% or so decrease in amplitude? Do we have more examples of how other people solved this? Of course 74F logic is relatively slow, and not usually terminated.
[quote author="miro"]Alm, yes you are right, the Tektronix input will be then ~kohm region (there is a diode from base to Vcc as well which lowers the base-emitor impedance by ~half for higher signal levels I would say). [/quote] As far as I can see they're just clamping diodes, so they shouldn't pass much current below 5V+Vf or so.
[quote author="miro"]Moreover the cable's impedance needs to be known as well. The above picture 1 shows the theory when unmatched (maybe the resistive part of the TL is <<0.3ohm with solid wire, but it will ring even more). [/quote] Is there such a thing as flying leads with a known impedance? That would only work for something like mictor connectors.
[quote author="miro"] The high-speed busses (50MHz signal with 1.1ns rise and fall time has an effective bandwith >300MHz) uses e.g. 220pulldown and 330pullup, or similar as the typical impedance of the ribbon cables is 110ohm (+/-). I2C bus runs ~1MHz max, so the matching is not so critical, but e.g. all current SPI flash, fram, ram, expanders run 25-66MHz. The uarts <3MHz. And when working with cheap fpga you may end up to 150200MHz.. So maybe a small OLS adapter with 4-8 matched lines (passive or active) for " a high speed measurements" would be nice to have (for people who know what they measure)..M.[/quote] Agreed that DC impedance is more important for slow buses. Capacitive loading tends to dominate at high edge rates, and the output impedance is usually lower for fast parts.
I checked how the big guys are doing it today. In the Agilent E5381A flying leads probes (which do 150ps edge rates) loading model, they show a DC impedance of about 20kohm. The Intronix LogicPort (500MS/s) has an input impedance of 200kohm. I don't trust them as much as Agilent, and I don't know about its signal integrity, but they seem fairly competent, so it's probably fine.
So even at several GHz, the big guys still use a high(ish) input impedance, but I'm not sure what tricks they employ, they may use resistive wire to damp ringing, for example. So I don't see the need to go to 200ohm at 100MHz or so. But I'm not enough of an RF wizard to design one, so I would look for more examples (preferably with more bandwidth).
[quote author="miro"]Alm, as far as I can see the Tektronics schematics shows ~150-200ohm input impedancies and the probe shall run up to 50MHz.[/quote] The series resistors are about 200ohm, but they are connected to the base of the input transistors, so the total impedance to ground is much higher. They don't specify the resistive part, although the capacitance is dominant at anything approaching high frequencies anyway. Note that it's a pretty old design (when TTL and ECL were current), so a modern design would probably look different. It was just the first schematic I found.
I agree that it's a good idea to pay more attention to the signal integrity/RF side, but the 200ohm impedance halves the amplitude, which will break almost any logic circuit (V[sub:]OL[/sub:] / 2 << V[sub:]IL[/sub:] all logic families I know).
200ohm is at least two orders of magnitude too low in my opinion, we're not in GHz territory where there's no such thing as a high-impedance input, a 200MHz high(ish)-impedance input is quite feasible IMO. One example were a higher input impedance would be necessary is with open collector/drain outputs (eg. I[sup:]2[/sup:]C), you want your input impedance to be significantly higher than the pull-up resistors.
[quote author="jack.gassett"]When I think back, I looked at some of the documentation of the high end Logic Analyzers to try and determine what they did. From what I remember, and this might be wrong since this was a while back, I thought they had RC networks in their high speed probes. So worse case scenario I would recommend picking up some high speed probes off ebay or something.[/quote] I believe they used passive pods for the early LAs, and moved to active pods in the seventies or so (probably for speed reasons). One pod manual with schematics is this one for the P6462/6452 (5MB PDF), these are active pods. LA inputs are typically in the order of 100kohm in parallel with a few pF of capacitance, so no impedance matching or transmission lines, but you do want to optimize signal integrity, and minimize reflections. It's probably fairly similar to an oscilloscope input, which is basically the same (except higher impedance and higher capacitance, and you don't need the switchable attenuator/amplifier).