1
Messages
This section allows you to view all Messages made by this member. Note that you can only see Messages made in areas you currently have access to.
Messages - steamraven
2
Open Bench Logic Sniffer / Re: Advanced Triggers
Example (A or (B and TIM1))
One mapping (of many) would be A -> A, B-> E, TIM1 to TIM1
Code: [Select]
A---|It basically is a synthisis problem: how do I configure a base circuit G such that for all inputs, G is equivalent to a function F?
A -------------|
B---| |
|
C------| |
0-----------|
Edge1--| |
|--------OR--------|
D----------| | |
0-------| OR---------------------------- output
Range1-----| | |
| |
E(B)-------| | (0 from other mid lut)
AND -----|
Tim1-------|
I have looked into using boolean satisfiability for logic synthesis, and this works if you only have like 4 inputs, but when you get to the full 16 inputs, the problem is has over 2^16 terms solving for 2^100 configuration bits. not fun.
Once I have this mapping, I can use dogbody's info to upload into the OLS
3
Client software / Re: Defining buses, advanced trigger
4
Open Bench Logic Sniffer / Re: FIFO wing to increase sample depth?
5
Open Bench Logic Sniffer / Advanced Triggers
Given a boolean equation: A or (B and TIM1)
how can we map this to the trigger sums in the advanced trigger? This seems very similar to FPGA synthesis. Does anyone have any pointers for me on where to look for more information?
Thanks,
Matt
6
Open Bench Logic Sniffer / Trigger State Machine
First, the Goal:
To create a full state machine with transitions controlled by internal triggers and external trigger while maintaining compatibility with the sump protocol and operation.
To start I will list the sump operation that I need to maintain. This is mainly from what I see in the code. If there are other constraints, please let me know. I am not changing how the triggers detect conditions, just what they do when found. Thus I will not describe serial vs complex and demux and such. These will stay the same.
Internal Triggers (4)
Trigger can either immediately start capture or upgrade trigger level by 1
Trigger can optionally delay for a certain number of clock cycles
After delay, trigger either starts capture or upgrades trigger level by 1
There is no check of continuing trigger condition
Triggers are not retriggerable
trigger is "armed" one cycle after ARM goes high
trigger goes to off state after signaling and stays off until ARM goes high
Trigger signals 1 cycle after trigger condition
Trigger only signals if trigger level is equal to or greater than configured level
Defaults:
0 delay
Match (upgrade level) not start
trigger on level 0 and higher
External Trigger
Immediately initiates run
Trigger State
4 trigger levels (0 - 3)
level 0 on arm
level goes up by 1 on match from internal triggers
level rolls over after 3
1 run level.
Sump protocol
set trigger config
delay
trigger level
channel for serial (Not needed)
serial flag (not needed)
start flag
So I want my design to maintain the above behavior, especially the configuration commands.
More to follow....
7
Open Bench Logic Sniffer / Re: Timed Triggers
Is this of actual interest to anybody here?
Matt
8
Open Bench Logic Sniffer / Re: demux flag?
9
Open Bench Logic Sniffer / demux flag?
Thanks,
Matt
10
Open Bench Logic Sniffer / Re: Timed Triggers
Mask: 11111111111111111111111111111111
value 01111111111111111111111111111111
Unfortunately, I cannot make use of the next levels.
It would be nice if you could specify more of a state machine for the triggers.
11
Open Bench Logic Sniffer / Timed Triggers
I see there is a delay setting in complex triggers and the protocol docs say
"delay: If a match occures, the action of the stage is delayed by the given number of samples"
But i am still confused how to use it for what I want. Any ideas?
12
Open Bench Logic Sniffer / Re: Test package: New SPI routing, Winbond ROM support
does all communication now happens over the DataFlash SPI-breakout pins on the pcb? That would make it quite easy to control the OLS from some custom SPI-Master hardware. (OLS run on batteries, with wireless network access? You can't buy that anywhere on this planet I think!)
[/quote]
Couldn't you also use the extra UART on the PIC? I believe it is brought to a header. You would need a custom pic firmware, but might be easier than tapping the pins on the PIC.
Matt
13
Open Bench Logic Sniffer / Re: OLS Availability
I look forward to playing with it. Regarding the papillo, I think having the LAX being synced to the OLS would be very beneficial. I for one am primarily looking for a logic analyzer, but I would definably pay more, if I could also get a nice FPGA development board.
Thanks for all the hard work in making this possible!
Matt
14
Open Bench Logic Sniffer / OLS Availability
Are there different revisions? What is the current revision?
I also noticed there is a logic analyzer project (lax) at gadget factory that runs on the papillo one (butterfly one) boards. How different is this from the OLS codebase?
Cheers,
Matt