[quote author="Torrentula"]It seems like I got lucky to download and reupload the modified bitstream to my server as it does have some uses.[/quote] i took it down just cause the name was misleading - it said jtagkey when it most certainly wasn't. the bbv3-passthrough.svf should be identical (let me know if you have trouble with it). Glad it's useful!!
[quote author="Torrentula"]I am already linking to the thread, may I reupload that .zip to my server so that I can link to a known good version (preventing dead link problem)? Of course I will attribute you for making those changes ;)[/quote] Post away, i copied the license file from the svn into the zip since everything is derived from that code to begin with.
Marcelo, i posted my verilog files on the BBv3 stuck at 1 thread, but figured out my problem was actually my urjtag command. after flashing the jtagkey file:
Perhaps this is or isn't your issue, if not post a log and i'll see if i can help at all.
I don't have a BBv4 to test anything but i built my tested bbv3 files for the bbv4 hardware and attached them. bbv4-jtaglink is logically identical to the standard jtaglink svf. bbv4-passthrough passes through all jtag signals.
tells urjtag to use a generic ft2232 wired straight-through to a jtag port. The pid/vid is necessary to tell it which device. urjtag doesn't properly set the jtagkey compatible enables and so tms/tck don't make it through.
tells it to use the jtagkey driver, which will properly toggle the enables and work properly. pid/vid are required since they do not match the jtagkey pid/vid
jtag> jtag> //write ian's buffer logic to the cpld using 2232 driver to interface 1 jtag> jtag> cable ft2232 pid=0x6010 vid=0x0403 interface=1 Connected to libftdi driver. jtag> detect IR length: 8 Chain length: 1 Device Id: 00000110111000011100000010010011 (0x06E1C093) Manufacturer: Xilinx (0x093) Part(0): xc2c32a-vq44 (0x6E1C) Stepping: 0 Filename: /usr/share/urjtag/xilinx/xc2c32a-vq44/xc2c32a-vq44 jtag> svf BBV3-JTAGkey-selftest-v1.1.svf stop progress detail: Parsing 660/664 ( 99%)detail: detail: Scanned device output matched expected TDO values. jtag> jtag> ///write your target with the jtagkey driver to interface 0 jtag> jtag> cable jtagkey pid=0x6010 vid=0x0403 interface=0 Connected to libftdi driver. jtag> detect IR length: 8 Chain length: 1 Device Id: 00000110111001011110000010010011 (0x06E5E093) Manufacturer: Xilinx (0x093) Part(0): XC2C64-VQ44 (0x6E5E) Stepping: 0 Filename: /usr/share/urjtag/xilinx/xc2c64a-vq44/xc2c64a-vq44 jtag> svf Verilog-CPLDIntro2Ledbutton.svf stop progress
So, i'll delete my file above and post several files here, including bbv3-passthrough.svf that will allow you to use it as a simple ftdi cable, a selftest-free bbv3-Jtagkey.svf tested with urjtag, and xilinx files to build them -joe
Programming the buffer logic went fine for me. Trying to program anything else got TDO stuck at errors.
I tried the svf posted here and any others i was able to find, nothing worked. Downloaded the source and built my own svf, still no. Started a xilinx project from scratch and copied pieces from the verilog project, still nothing different.
shorting TDO to vcc/ground with a wire got TDO stuck at 1/0, so i knew it was sort of working, but i wasn't seeing anything happen on the output signals. Modified the rtl to map FT_JTAG_OE to the LED and saw it was always high.
So, i removed the output enable logic, wrote the svf, and now my bus blaster works great with urjtag. I don't pretend to know how everything is supposed to work (particularly the software) so someone please let me know if i did something i shouldn't have by removing the output enable.
Otherwise, svf attached. good luck. Log shows writing my buffer logic then writing one of the tutorial files to my cpld dev board (er, well, actually to a xbox360 glitch chip, AKA my $3 cpld development board.)
