Will I never learn. Saw this summary: The 1.2V Spartan -3 family of Field-Programmable Gate Arrays is ... Endurance of 10000 program/erase cycles. - Program/erase over full commercial voltage ...
on a google search result on a Xilinx.com page and didn't even think to look at the full context. They're talking about the XC9500.
I've been porting the XAPP058 code over to an arduino, hopefully I'll be able to load configurations from an SD card or over ethernet in two weeks once exams are over.
Robots: The final target is a chip more along the lines of a Spartan 3, with an Npe of >= 10k cycles. CPLDs are just a start, cheaper chips. Even for 1000 cycles though, that still lets you have some fun. Thanks for the heads up though, I had the number from FPGAs in my head and forgot to look at the number for CPLDs.
It is. Pity it was more expensive than the through hole version.
Taking the photo showed me I need a better way of taking macro shots. Thanks for posting that description of your setup. I'll be trying to make something similar as I can see more boards coming down the line that need photos. Not to mention a backlog of projects that would be fun to have archived.
Posting in the CPLD forum a few days ago reminded me that I never posted a photo of the Bus Pirate v3c that I assembled after getting a free PCB back a while ago. Took me until this week to find a pic programmer though. Hopefully I'll get a chance to start using it this weekend. The solder job on the ICs is a little sad, but all checks out.
Ofcourse, after posting I found this Xilinx application note, XAPP058. Xilinx In-System Programming Using an Embedded Microcontroller
The CPLD/FPGA designs are processed into a XSVF File. (Xilinx?) Serial Vector Format. This can be stored in memory on the PCB and then an XSVF interpreter on the processor feeds the configuration over JTAG. The files aren't prohibitively large, <= 1MB even for large devices.
There's a reference C design for an XSVF Interpreter so I'll be starting there.
I can't post links yet so sorry about the format. www (dot) xilinx (dot) com/support/documentation/application_notes/xapp058.pdf https:// secure (dot) xilinx (dot) com/webreg/clickthrough.do?cid=113970&license=RefDesLicense
I'm interested in programming a CPLD (Coolrunner-II or Altera EPM3064ALC44-10) with a microcontroller (Arduino or Netduino). The idea is to load custom logic on demand in the field.
There are posts around the internet that this is possible (just have to interface with the JTAG connection) but I haven't found working code. I'll be looking into this once the summer starts but wanted to find out if anyone has seen a working implementation or is interested in working on this.
